from nmigen import *

class rvfi_insn(Elaboratable):
    def __init__(self):
        # Input ports
        self.rvfi_valid = Signal(1)
        self.rvfi_insn = Signal(32)
        self.rvfi_pc_rdata = Signal(32)
        self.rvfi_rs1_rdata = Signal(32)
        self.rvfi_rs2_rdata = Signal(32)
        self.rvfi_mem_rdata = Signal(32)

        # Output ports
        self.spec_valid = Signal(1)
        self.spec_trap = Signal(1)
        self.spec_rs1_addr = Signal(5)
        self.spec_rs2_addr = Signal(5)
        self.spec_rd_addr = Signal(5)
        self.spec_rd_wdata = Signal(32)
        self.spec_pc_wdata = Signal(32)
        self.spec_mem_addr = Signal(32)
        self.spec_mem_rmask = Signal(4)
        self.spec_mem_wmask = Signal(4)
        self.spec_mem_wdata = Signal(32)
    def ports(self):
        input_ports = [
            self.rvfi_valid,
            self.rvfi_insn,
            self.rvfi_pc_rdata,
            self.rvfi_rs1_rdata,
            self.rvfi_rs2_rdata,
            self.rvfi_mem_rdata
        ]
        output_ports = [
            self.spec_valid,
            self.spec_trap,
            self.spec_rs1_addr,
            self.spec_rs2_addr,
            self.spec_rd_addr,
            self.spec_rd_wdata,
            self.spec_pc_wdata,
            self.spec_mem_addr,
            self.spec_mem_rmask,
            self.spec_mem_wmask,
            self.spec_mem_wdata
        ]
        return input_ports + output_ports
    def elaborate(self, platform):
        m = Module()

        return m