from nmigen import *
from nmigen.hdl.ast import *

class rvfi_channel(Elaboratable):
    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
        self.rvfi_valid = Signal(1)
        self.rvfi_order = Signal(64)
        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
        self.rvfi_trap = Signal(1)
        self.rvfi_halt = Signal(1)
        self.rvfi_intr = Signal(1)
        self.rvfi_mode = Signal(2)
        self.rvfi_ixl = Signal(2)
        self.rvfi_rs1_addr = Signal(5)
        self.rvfi_rs2_addr = Signal(5)
        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_rd_addr = Signal(5)
        self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
        self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
        self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
    def ports(self):
        input_ports = [
            self.rvfi_valid,
            self.rvfi_order,
            self.rvfi_insn,
            self.rvfi_trap,
            self.rvfi_halt,
            self.rvfi_intr,
            self.rvfi_mode,
            self.rvfi_ixl,
            self.rvfi_rs1_addr,
            self.rvfi_rs2_addr,
            self.rvfi_rs1_rdata,
            self.rvfi_rs2_rdata,
            self.rvfi_rd_addr,
            self.rvfi_rd_wdata,
            self.rvfi_pc_rdata,
            self.rvfi_pc_wdata,
            self.rvfi_mem_addr,
            self.rvfi_mem_rmask,
            self.rvfi_mem_wmask,
            self.rvfi_mem_rdata,
            self.rvfi_mem_wdata
        ]
        output_ports = []
        return input_ports + output_ports
    def elaborate(self, platform):
        m = Module()

        valid = Signal(1)
        m.d.comb += valid.eq(self.rvfi_valid)
        order = Signal(64)
        m.d.comb += order.eq(self.rvfi_order)
        insn = Signal(self.RISCV_FORMAL_ILEN)
        m.d.comb += insn.eq(self.rvfi_insn)
        trap = Signal(1)
        m.d.comb += trap.eq(self.rvfi_trap)
        halt = Signal(1)
        m.d.comb += halt.eq(self.rvfi_halt)
        intr = Signal(1)
        m.d.comb += intr.eq(self.rvfi_intr)
        mode = Signal(2)
        m.d.comb += mode.eq(self.rvfi_mode)
        ixl = Signal(2)
        m.d.comb += ixl.eq(self.rvfi_ixl)

        rs1_addr = Signal(5)
        m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr)
        rs2_addr = Signal(5)
        m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr)
        rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata)
        rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata)
        rd_addr = Signal(5)
        m.d.comb += rd_addr.eq(self.rvfi_rd_addr)
        rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata)
        pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
        pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata)

        mem_addr = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += mem_addr.eq(self.rvfi_mem_addr)
        mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
        m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask)
        mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
        m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask)
        mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata)
        mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata)

        return m