from .insn_rv32i_i_type import * """ JALR instruction """ class InsnJalr(InsnRV32IIType): def elaborate(self, platform): m = super().elaborate(platform) if self.params.csr_misa: m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) m.d.comb += self.spec_csr_misa_rmask.eq(4) m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0) else: m.d.comb += self.misa_ok.eq(1) if self.params.compressed: m.d.comb += self.ialign16.eq(1) else: m.d.comb += self.ialign16.eq(0) next_pc = Signal(self.params.xlen) m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) m.d.comb += self.spec_rd_addr.eq(self.insn_rd) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) return m