from nmigen import *
from nmigen.asserts import *

"""
Causal Check
"""

class CausalCheck(Elaboratable):
    def __init__(self):
        # Input ports
        self.reset = Signal(1)
        self.check = Signal(1)
        self.rvfi_valid = Signal(1)
        self.rvfi_rd_addr = Signal(5)
        self.rvfi_order = Signal(64)
        self.rvfi_rs1_addr = Signal(5)
        self.rvfi_rs2_addr = Signal(5)

    def ports(self):
        input_ports = [
            self.reset,
            self.check,
            self.rvfi_valid,
            self.rvfi_rd_addr,
            self.rvfi_order,
            self.rvfi_rs1_addr,
            self.rvfi_rs2_addr
        ]
        return input_ports

    def elaborate(self, platform):
        m = Module()

        insn_order = AnyConst(64)
        register_index = AnyConst(5)
        found_non_causal = Signal(1, reset=0)

        with m.If(self.reset):
            m.d.sync += found_non_causal.eq(0)
        with m.Else():
            with m.If(self.check):
                m.d.comb += Assume(register_index != 0)
                m.d.comb += Assume(self.rvfi_valid)
                m.d.comb += Assume(register_index == self.rvfi_rd_addr)
                m.d.comb += Assume(insn_order == self.rvfi_order)
                m.d.comb += Assert(~found_non_causal)
            with m.Else():
                with m.If(self.rvfi_valid & (self.rvfi_order > insn_order) & ((register_index == self.rvfi_rs1_addr) | (register_index == self.rvfi_rs2_addr))):
                    m.d.sync += found_non_causal.eq(1)

        return m