Apply more PEP 8 guidelines, remove hacks and reduce code duplication #3
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@ -4,14 +4,14 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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## Breakdown
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| Directory | Description |
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| File/Directory | Description |
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| --- | --- |
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| `shell.nix` | [nix-shell](https://nixos.wiki/wiki/Development_environment_with_nix-shell) configuration file |
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| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
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| `rvfi/insns` | Supported RISC-V instructions and ISAs |
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| `rvfi/checks` | Checks for RISC-V compliant cores |
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| `rvfi/cores` | Cores currently tested against this port of riscv-formal |
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| `rvfi/cores/minerva` | Tests for the Minerva core |
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| `rvfi/cores/minerva/verify.py` | Verification tasks for the Minerva core |
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## Running the Verification
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@ -15,6 +15,7 @@ class CausalCheck(Elaboratable):
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self.rvfi_order = Signal(64)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs2_addr = Signal(5)
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def ports(self):
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input_ports = [
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self.reset,
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@ -26,6 +27,7 @@ class CausalCheck(Elaboratable):
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self.rvfi_rs2_addr
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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@ -6,13 +6,9 @@ Instruction Check
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"""
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class InsnCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, insn_model, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
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self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
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self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
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def __init__(self, params, insn_model, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Instruction under test
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self.insn_model = insn_model
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@ -26,7 +22,7 @@ class InsnCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_insn = Signal(self.params.ilen)
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self.rvfi_trap = Signal(1)
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self.rvfi_halt = Signal(1)
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self.rvfi_intr = Signal(1)
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@ -34,22 +30,23 @@ class InsnCheck(Elaboratable):
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self.rvfi_ixl = Signal(2)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs2_addr = Signal(5)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_rd_addr = Signal(5)
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self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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if self.RISCV_FORMAL_CSR_MISA:
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self.rvfi_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_wmask = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rd_wdata = Signal(self.params.xlen)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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self.rvfi_mem_addr = Signal(self.params.xlen)
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self.rvfi_mem_rmask = Signal(int(self.params.xlen // 8))
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self.rvfi_mem_wmask = Signal(int(self.params.xlen // 8))
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self.rvfi_mem_rdata = Signal(self.params.xlen)
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self.rvfi_mem_wdata = Signal(self.params.xlen)
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if self.params.csr_misa:
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self.rvfi_csr_misa_rmask = Signal(self.params.xlen)
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self.rvfi_csr_misa_wmask = Signal(self.params.xlen)
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self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
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self.rvfi_csr_misa_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -76,7 +73,7 @@ class InsnCheck(Elaboratable):
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self.rvfi_mem_rdata,
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self.rvfi_mem_wdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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input_ports.extend([
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self.rvfi_csr_misa_rmask,
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self.rvfi_csr_misa_wmask,
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@ -84,78 +81,54 @@ class InsnCheck(Elaboratable):
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self.rvfi_csr_misa_wdata
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])
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return input_ports
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def elaborate(self, platform):
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m = Module()
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valid = Signal(1)
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m.d.comb += valid.eq((~self.reset) & self.rvfi_valid)
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insn = Signal(self.RISCV_FORMAL_ILEN)
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m.d.comb += insn.eq(self.rvfi_insn)
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trap = Signal(1)
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m.d.comb += trap.eq(self.rvfi_trap)
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halt = Signal(1)
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m.d.comb += halt.eq(self.rvfi_halt)
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intr = Signal(1)
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m.d.comb += intr.eq(self.rvfi_intr)
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rs1_addr = Signal(5)
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m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr)
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rs2_addr = Signal(5)
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m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr)
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rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata)
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rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata)
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rd_addr = Signal(5)
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m.d.comb += rd_addr.eq(self.rvfi_rd_addr)
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rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata)
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pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
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pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata)
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insn = self.rvfi_insn
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trap = self.rvfi_trap
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halt = self.rvfi_halt
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intr = self.rvfi_intr
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rs1_addr = self.rvfi_rs1_addr
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rs2_addr = self.rvfi_rs2_addr
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rs1_rdata = self.rvfi_rs1_rdata
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rs2_rdata = self.rvfi_rs2_rdata
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rd_addr = self.rvfi_rd_addr
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rd_wdata = self.rvfi_rd_wdata
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pc_rdata = self.rvfi_pc_rdata
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pc_wdata = self.rvfi_pc_wdata
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mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_addr.eq(self.rvfi_mem_addr)
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mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask)
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mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask)
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mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata)
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mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata)
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mem_addr = self.rvfi_mem_addr
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mem_rmask = self.rvfi_mem_rmask
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mem_wmask = self.rvfi_mem_wmask
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mem_rdata = self.rvfi_mem_rdata
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mem_wdata = self.rvfi_mem_wdata
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if self.RISCV_FORMAL_CSR_MISA:
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csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += csr_misa_rdata.eq(self.rvfi_csr_misa_rdata)
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csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += csr_misa_rmask.eq(self.rvfi_csr_misa_rmask)
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spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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if self.params.csr_misa:
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csr_misa_rdata = self.rvfi_csr_misa_rdata
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csr_misa_rmask = self.rvfi_csr_misa_rmask
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spec_csr_misa_rmask = Signal(self.params.xlen)
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spec_valid = Signal(1)
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spec_trap = Signal(1)
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spec_rs1_addr = Signal(5)
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spec_rs2_addr = Signal(5)
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spec_rd_addr = Signal(5)
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spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_rd_wdata = Signal(self.params.xlen)
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spec_pc_wdata = Signal(self.params.xlen)
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spec_mem_addr = Signal(self.params.xlen)
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spec_mem_rmask = Signal(int(self.params.xlen // 8))
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spec_mem_wmask = Signal(int(self.params.xlen // 8))
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spec_mem_wdata = Signal(self.params.xlen)
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rs1_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN)
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rs1_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs1_rdata_or_zero.eq(Mux(spec_rs1_addr != 0, rs1_rdata, 0))
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rs2_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN)
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rs2_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs2_rdata_or_zero.eq(Mux(spec_rs2_addr != 0, rs2_rdata, 0))
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try:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA)
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except:
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try:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED=self.RISCV_FORMAL_COMPRESSED)
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except:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM=self.RISCV_FORMAL_ALIGNED_MEM)
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m.submodules.insn_spec = insn_spec = self.insn_model(self.params)
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m.d.comb += insn_spec.rvfi_valid.eq(valid)
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m.d.comb += insn_spec.rvfi_insn.eq(insn)
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@ -164,7 +137,7 @@ class InsnCheck(Elaboratable):
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(rs2_rdata_or_zero)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(mem_rdata)
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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m.d.comb += insn_spec.rvfi_csr_misa_rdata.eq(csr_misa_rdata)
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m.d.comb += spec_csr_misa_rmask.eq(insn_spec.spec_csr_misa_rmask)
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@ -208,7 +181,7 @@ class InsnCheck(Elaboratable):
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m.d.comb += Assert(rd_wdata == 0)
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m.d.comb += Assert(mem_wmask == 0)
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with m.Else():
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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m.d.comb += Assert((spec_csr_misa_rmask & csr_misa_rmask) == spec_csr_misa_rmask)
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with m.If(rs1_addr == 0):
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@ -231,7 +204,7 @@ class InsnCheck(Elaboratable):
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with m.If(spec_mem_wmask | spec_mem_rmask):
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m.d.comb += Assert(self.rvformal_addr_eq(spec_mem_addr, mem_addr))
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for i in range(int(self.RISCV_FORMAL_XLEN // 8)):
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for i in range(int(self.params.xlen // 8)):
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with m.If(spec_mem_wmask[i]):
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m.d.comb += Assert(mem_wmask[i])
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m.d.comb += Assert(spec_mem_wdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8])
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@ -6,9 +6,9 @@ PC Backward Check
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"""
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class PcBwdCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Address validity and equality
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self.rvformal_addr_valid = rvformal_addr_valid
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@ -19,8 +19,9 @@ class PcBwdCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -31,14 +32,15 @@ class PcBwdCheck(Elaboratable):
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self.rvfi_pc_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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expect_pc = Signal(self.RISCV_FORMAL_XLEN)
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expect_pc = Signal(self.params.xlen)
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expect_pc_valid = Signal(1, reset=0)
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pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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pc_wdata = Signal(self.params.xlen)
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m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata)
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with m.If(self.reset):
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@ -6,9 +6,9 @@ PC Forward Check
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"""
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class PcFwdCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Address validity and equality
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self.rvformal_addr_valid = rvformal_addr_valid
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@ -19,8 +19,9 @@ class PcFwdCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -31,14 +32,15 @@ class PcFwdCheck(Elaboratable):
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self.rvfi_pc_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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expect_pc = Signal(self.RISCV_FORMAL_XLEN)
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expect_pc = Signal(self.params.xlen)
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expect_pc_valid = Signal(1, reset=0)
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pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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pc_rdata = Signal(self.params.xlen)
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m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
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with m.If(self.reset):
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@ -6,9 +6,9 @@ Register Check
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"""
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class RegCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params):
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# Core-specific parameters
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self.params = params
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# Input ports
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self.reset = Signal(1)
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@ -16,11 +16,12 @@ class RegCheck(Elaboratable):
|
|||
self.rvfi_valid = Signal(1)
|
||||
self.rvfi_order = Signal(64)
|
||||
self.rvfi_rs1_addr = Signal(5)
|
||||
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs1_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rs2_addr = Signal(5)
|
||||
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs2_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rd_addr = Signal(5)
|
||||
self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rd_wdata = Signal(self.params.xlen)
|
||||
|
||||
def ports(self):
|
||||
input_ports = [
|
||||
self.reset,
|
||||
|
@ -35,12 +36,13 @@ class RegCheck(Elaboratable):
|
|||
self.rvfi_rd_wdata
|
||||
]
|
||||
return input_ports
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
insn_order = AnyConst(64)
|
||||
register_index = AnyConst(5)
|
||||
register_shadow = Signal(self.RISCV_FORMAL_XLEN, reset=0)
|
||||
register_shadow = Signal(self.params.xlen, reset=0)
|
||||
register_written = Signal(1, reset=0)
|
||||
|
||||
with m.If(self.reset):
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -89,14 +89,14 @@ Below is a list of instructions currently supported by this port of the riscv-fo
|
|||
|
||||
- `IsaRV32I`: RV32I Base ISA
|
||||
|
||||
## Core-specific constants
|
||||
## Core-specific parameters
|
||||
|
||||
The following core-specific constants are currently supported:
|
||||
The following core-specific parameters are currently supported:
|
||||
|
||||
| Constant | Description | Valid value(s) | Supported by instruction(s) | Supported by ISA(s) |
|
||||
| --- | --- | --- | --- | --- |
|
||||
| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
|
||||
| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
|
||||
| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I |
|
||||
| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | RV32I |
|
||||
| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | RV32I |
|
||||
| Parameter | Description | Valid value(s) |
|
||||
| --- | --- | --- |
|
||||
| `params.ilen` | Max length of instruction retired by core | `32` |
|
||||
| `params.xlen` | Width of integer registers | `32` |
|
||||
| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
|
||||
| `params.compressed` | Support for compressed instructions | `True`, `False` |
|
||||
| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
|
||||
|
|
|
@ -1,45 +1,42 @@
|
|||
from nmigen import *
|
||||
|
||||
"""
|
||||
Insn.py
|
||||
Class for generic RISC-V instructions
|
||||
General RISC-V Instruction
|
||||
"""
|
||||
|
||||
class Insn(Elaboratable):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
# Core-specific constants
|
||||
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
|
||||
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
|
||||
self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
|
||||
def __init__(self, params):
|
||||
# Core-specific parameters
|
||||
self.params = params
|
||||
|
||||
# RVFI input ports
|
||||
self.rvfi_valid = Signal(1)
|
||||
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
|
||||
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_insn = Signal(self.params.ilen)
|
||||
self.rvfi_pc_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rs1_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rs2_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_mem_rdata = Signal(self.params.xlen)
|
||||
if self.params.csr_misa:
|
||||
self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
|
||||
|
||||
# RVFI output ports
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
|
||||
if self.params.csr_misa:
|
||||
self.spec_csr_misa_rmask = Signal(self.params.xlen)
|
||||
self.spec_valid = Signal(1)
|
||||
self.spec_trap = Signal(1)
|
||||
self.spec_rs1_addr = Signal(5)
|
||||
self.spec_rs2_addr = Signal(5)
|
||||
self.spec_rd_addr = Signal(5)
|
||||
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||||
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||||
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_rd_wdata = Signal(self.params.xlen)
|
||||
self.spec_pc_wdata = Signal(self.params.xlen)
|
||||
self.spec_mem_addr = Signal(self.params.xlen)
|
||||
self.spec_mem_rmask = Signal(int(self.params.xlen // 8))
|
||||
self.spec_mem_wmask = Signal(int(self.params.xlen // 8))
|
||||
self.spec_mem_wdata = Signal(self.params.xlen)
|
||||
|
||||
# Additional wires and registers
|
||||
self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
|
||||
self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.insn_padding = Signal(self.params.ilen)
|
||||
self.insn_imm = Signal(self.params.xlen)
|
||||
self.insn_funct7 = Signal(7)
|
||||
self.insn_funct6 = Signal(6)
|
||||
self.insn_shamt = Signal(6)
|
||||
|
@ -50,6 +47,7 @@ class Insn(Elaboratable):
|
|||
self.insn_opcode = Signal(7)
|
||||
self.misa_ok = Signal(1)
|
||||
self.ialign16 = Signal(1)
|
||||
|
||||
def ports(self):
|
||||
input_ports = [
|
||||
self.rvfi_valid,
|
||||
|
@ -59,7 +57,7 @@ class Insn(Elaboratable):
|
|||
self.rvfi_rs2_rdata,
|
||||
self.rvfi_mem_rdata
|
||||
]
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
input_ports.append(self.rvfi_csr_misa_rdata)
|
||||
output_ports = [
|
||||
self.spec_valid,
|
||||
|
@ -74,9 +72,10 @@ class Insn(Elaboratable):
|
|||
self.spec_mem_wmask,
|
||||
self.spec_mem_wdata
|
||||
]
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
output_ports.append(self.spec_csr_misa_rmask)
|
||||
return input_ports + output_ports
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ ADD instruction
|
|||
"""
|
||||
|
||||
class InsnAdd(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b000, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b000, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ ADDI instruction
|
|||
"""
|
||||
|
||||
class InsnAddi(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ AND instruction
|
|||
"""
|
||||
|
||||
class InsnAnd(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b111, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b111, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ ANDI instruction
|
|||
"""
|
||||
|
||||
class InsnAndi(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b111)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b111)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ AUIPC instruction
|
|||
"""
|
||||
|
||||
class InsnAuipc(InsnRV32IUType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0010111)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0010111)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,12 +5,13 @@ BEQ instruction
|
|||
"""
|
||||
|
||||
class InsnBeq(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,12 +5,13 @@ BGE instruction
|
|||
"""
|
||||
|
||||
class InsnBge(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b101)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b101)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,12 +5,13 @@ BGEU instruction
|
|||
"""
|
||||
|
||||
class InsnBgeu(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b111)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b111)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,12 +5,13 @@ BLT instruction
|
|||
"""
|
||||
|
||||
class InsnBlt(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b100)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b100)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,12 +5,13 @@ BLTU instruction
|
|||
"""
|
||||
|
||||
class InsnBltu(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b110)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b110)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,12 +5,13 @@ BNE instruction
|
|||
"""
|
||||
|
||||
class InsnBne(InsnRV32ISBType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b001)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b001)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(Mux(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
|
||||
m.d.comb += self.spec_pc_wdata.eq(next_pc)
|
||||
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
|
||||
|
|
|
@ -5,26 +5,23 @@ JAL instruction
|
|||
"""
|
||||
|
||||
class InsnJal(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(4)
|
||||
m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
if self.RISCV_FORMAL_COMPRESSED:
|
||||
if self.params.compressed:
|
||||
m.d.comb += self.ialign16.eq(1)
|
||||
else:
|
||||
m.d.comb += self.ialign16.eq(0)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm)
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
|
||||
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||||
|
|
|
@ -5,24 +5,21 @@ JALR instruction
|
|||
"""
|
||||
|
||||
class InsnJalr(InsnRV32IIType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(4)
|
||||
m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
if self.RISCV_FORMAL_COMPRESSED:
|
||||
if self.params.compressed:
|
||||
m.d.comb += self.ialign16.eq(1)
|
||||
else:
|
||||
m.d.comb += self.ialign16.eq(0)
|
||||
|
||||
next_pc = Signal(self.RISCV_FORMAL_XLEN)
|
||||
next_pc = Signal(self.params.xlen)
|
||||
m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1)
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
|
|
|
@ -5,5 +5,5 @@ LB instruction
|
|||
"""
|
||||
|
||||
class InsnLb(InsnRV32IITypeLoad):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1, True)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000, 1, True)
|
||||
|
|
|
@ -5,5 +5,5 @@ LBU instruction
|
|||
"""
|
||||
|
||||
class InsnLbu(InsnRV32IITypeLoad):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b100, 1, False)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b100, 1, False)
|
||||
|
|
|
@ -5,5 +5,5 @@ LH instruction
|
|||
"""
|
||||
|
||||
class InsnLh(InsnRV32IITypeLoad):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2, True)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b001, 2, True)
|
||||
|
|
|
@ -5,5 +5,5 @@ LHU instruction
|
|||
"""
|
||||
|
||||
class InsnLhu(InsnRV32IITypeLoad):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b101, 2, False)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b101, 2, False)
|
||||
|
|
|
@ -5,8 +5,9 @@ LUI instruction
|
|||
"""
|
||||
|
||||
class InsnLui(InsnRV32IUType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0110111)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0110111)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,5 +5,5 @@ LW instruction
|
|||
"""
|
||||
|
||||
class InsnLw(InsnRV32IITypeLoad):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4, True)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b010, 4, True)
|
||||
|
|
|
@ -5,8 +5,9 @@ OR instruction
|
|||
"""
|
||||
|
||||
class InsnOr(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b110, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b110, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ ORI instruction
|
|||
"""
|
||||
|
||||
class InsnOri(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b110)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b110)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,13 +5,14 @@ RV32I I-Type Instruction (Arithmetic Variation)
|
|||
"""
|
||||
|
||||
class InsnRV32IITypeArith(InsnRV32IIType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct3):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
def __init__(self, params, funct3):
|
||||
super().__init__(params)
|
||||
self.funct3 = funct3
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
|
|
|
@ -5,30 +5,30 @@ RV32I I-Type Instruction (Load Variation)
|
|||
"""
|
||||
|
||||
class InsnRV32IITypeLoad(InsnRV32IIType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
|
||||
def __init__(self, params, funct3, mask_shift, is_signed):
|
||||
super().__init__(params)
|
||||
self.funct3 = funct3
|
||||
self.mask_shift = mask_shift
|
||||
self.is_signed = is_signed
|
||||
self.addr = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.addr = Signal(self.params.xlen)
|
||||
self.result = Signal(8 * self.mask_shift)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
|
||||
if self.RISCV_FORMAL_ALIGNED_MEM:
|
||||
if self.params.aligned_mem:
|
||||
m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
|
||||
m.d.comb += self.result.eq(self.rvfi_mem_rdata >> (8 * (self.addr - self.spec_mem_addr)))
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||||
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
|
||||
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
|
||||
m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
|
||||
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||||
|
|
|
@ -5,20 +5,21 @@ RV32I I-Type Instruction (Shift Variation)
|
|||
"""
|
||||
|
||||
class InsnRV32IITypeShift(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct6, funct3):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
def __init__(self, params, funct6, funct3):
|
||||
super().__init__(params)
|
||||
self.funct6 = funct6
|
||||
self.funct3 = funct3
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.params.xlen == 64)))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
|
||||
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||||
|
|
|
@ -5,15 +5,16 @@ RV32I R-Type Instruction
|
|||
"""
|
||||
|
||||
class InsnRV32IRType(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct7, funct3, opcode):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
def __init__(self, params, funct7, funct3, opcode):
|
||||
super().__init__(params)
|
||||
self.funct7 = funct7
|
||||
self.funct3 = funct3
|
||||
self.opcode = opcode
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
|
|
|
@ -5,29 +5,29 @@ RV32I S-Type Instruction
|
|||
"""
|
||||
|
||||
class InsnRV32ISType(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
|
||||
def __init__(self, params, funct3, mask_shift):
|
||||
super().__init__(params)
|
||||
self.funct3 = funct3
|
||||
self.mask_shift = mask_shift
|
||||
self.addr = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.addr = Signal(self.params.xlen)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
|
||||
if self.RISCV_FORMAL_ALIGNED_MEM:
|
||||
if self.params.aligned_mem:
|
||||
m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
|
||||
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0100011))
|
||||
m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
|
||||
m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
|
||||
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
|
||||
m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.params.xlen // 8) - 1))
|
||||
m.d.comb += self.spec_mem_wmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
|
||||
m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (self.addr - self.spec_mem_addr)))
|
||||
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
|
||||
|
|
|
@ -5,22 +5,22 @@ RV32I SB-Type Instruction
|
|||
"""
|
||||
|
||||
class InsnRV32ISBType(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
|
||||
def __init__(self, params, funct3):
|
||||
super().__init__(params)
|
||||
self.funct3 = funct3
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(4)
|
||||
m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
|
||||
else:
|
||||
m.d.comb += self.misa_ok.eq(1)
|
||||
if self.RISCV_FORMAL_COMPRESSED:
|
||||
if self.params.compressed:
|
||||
m.d.comb += self.ialign16.eq(1)
|
||||
else:
|
||||
m.d.comb += self.ialign16.eq(0)
|
||||
|
|
|
@ -5,15 +5,16 @@ RV32I U-Type Instruction
|
|||
"""
|
||||
|
||||
class InsnRV32IUType(Insn):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, opcode):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
|
||||
def __init__(self, params, opcode):
|
||||
super().__init__(params)
|
||||
self.opcode = opcode
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
|
||||
m.d.comb += self.spec_csr_misa_rmask.eq(0)
|
||||
else:
|
||||
|
|
|
@ -5,5 +5,5 @@ SB instruction
|
|||
"""
|
||||
|
||||
class InsnSb(InsnRV32ISType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b000, 1)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000, 1)
|
||||
|
|
|
@ -5,5 +5,5 @@ SH instruction
|
|||
"""
|
||||
|
||||
class InsnSh(InsnRV32ISType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b001, 2)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b001, 2)
|
||||
|
|
|
@ -5,11 +5,12 @@ SLL instruction
|
|||
"""
|
||||
|
||||
class InsnSll(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b001, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b001, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
|
||||
return m
|
||||
|
|
|
@ -5,8 +5,9 @@ SLLI instruction
|
|||
"""
|
||||
|
||||
class InsnSlli(InsnRV32IITypeShift):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b001)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000000, 0b001)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ SLT instruction
|
|||
"""
|
||||
|
||||
class InsnSlt(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b010, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b010, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ SLTI instruction
|
|||
"""
|
||||
|
||||
class InsnSlti(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b010)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ SLTIU instruction
|
|||
"""
|
||||
|
||||
class InsnSltiu(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ SLTU instruction
|
|||
"""
|
||||
|
||||
class InsnSltu(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b011, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b011, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,11 +5,12 @@ SRA instruction
|
|||
"""
|
||||
|
||||
class InsnSra(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b101, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0100000, 0b101, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) # https://stackoverflow.com/a/25207042
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.params.xlen - Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) # https://stackoverflow.com/a/25207042
|
||||
|
||||
return m
|
||||
|
|
|
@ -5,11 +5,12 @@ SRAI instruction
|
|||
"""
|
||||
|
||||
class InsnSrai(InsnRV32IITypeShift):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b010000, 0b101)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b010000, 0b101)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> self.insn_shamt) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - self.insn_shamt)), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> self.insn_shamt) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.params.xlen - self.insn_shamt)), 0))
|
||||
|
||||
return m
|
||||
|
|
|
@ -5,11 +5,12 @@ SRL instruction
|
|||
"""
|
||||
|
||||
class InsnSrl(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b100, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
|
||||
return m
|
||||
|
|
|
@ -5,8 +5,9 @@ SRLI instruction
|
|||
"""
|
||||
|
||||
class InsnSrli(InsnRV32IITypeShift):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b000000, 0b101)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b000000, 0b101)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ SUB instruction
|
|||
"""
|
||||
|
||||
class InsnSub(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0100000, 0b000, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0100000, 0b000, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,5 +5,5 @@ SW instruction
|
|||
"""
|
||||
|
||||
class InsnSw(InsnRV32ISType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b010, 4)
|
||||
|
|
|
@ -5,8 +5,9 @@ XOR instruction
|
|||
"""
|
||||
|
||||
class InsnXor(InsnRV32IRType):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b0000000, 0b100, 0b0110011)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b0000000, 0b100, 0b0110011)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -5,8 +5,9 @@ XORI instruction
|
|||
"""
|
||||
|
||||
class InsnXori(InsnRV32IITypeArith):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):
|
||||
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, 0b100)
|
||||
def __init__(self, params):
|
||||
super().__init__(params, 0b100)
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
|
|
|
@ -41,38 +41,35 @@ RV32I Base ISA
|
|||
"""
|
||||
|
||||
class IsaRV32I(Elaboratable):
|
||||
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
|
||||
# Core-specific constants
|
||||
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
|
||||
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
|
||||
self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
|
||||
self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
|
||||
self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
|
||||
def __init__(self, params):
|
||||
# Core-specific parameters
|
||||
self.params = params
|
||||
|
||||
# Input ports
|
||||
self.rvfi_valid = Signal(1)
|
||||
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
|
||||
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.rvfi_insn = Signal(self.params.ilen)
|
||||
self.rvfi_pc_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rs1_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_rs2_rdata = Signal(self.params.xlen)
|
||||
self.rvfi_mem_rdata = Signal(self.params.xlen)
|
||||
if self.params.csr_misa:
|
||||
self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
|
||||
|
||||
# Output ports
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
|
||||
if self.params.csr_misa:
|
||||
self.spec_csr_misa_rmask = Signal(self.params.xlen)
|
||||
self.spec_valid = Signal(1)
|
||||
self.spec_trap = Signal(1)
|
||||
self.spec_rs1_addr = Signal(5)
|
||||
self.spec_rs2_addr = Signal(5)
|
||||
self.spec_rd_addr = Signal(5)
|
||||
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||||
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
|
||||
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
|
||||
self.spec_rd_wdata = Signal(self.params.xlen)
|
||||
self.spec_pc_wdata = Signal(self.params.xlen)
|
||||
self.spec_mem_addr = Signal(self.params.xlen)
|
||||
self.spec_mem_rmask = Signal(int(self.params.xlen // 8))
|
||||
self.spec_mem_wmask = Signal(int(self.params.xlen // 8))
|
||||
self.spec_mem_wdata = Signal(self.params.xlen)
|
||||
|
||||
def ports(self):
|
||||
input_ports = [
|
||||
self.rvfi_valid,
|
||||
|
@ -82,7 +79,7 @@ class IsaRV32I(Elaboratable):
|
|||
self.rvfi_rs2_rdata,
|
||||
self.rvfi_mem_rdata
|
||||
]
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
input_ports.append(self.rvfi_csr_misa_rdata)
|
||||
output_ports = [
|
||||
self.spec_valid,
|
||||
|
@ -97,51 +94,52 @@ class IsaRV32I(Elaboratable):
|
|||
self.spec_mem_wmask,
|
||||
self.spec_mem_wdata
|
||||
]
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
output_ports.append(self.spec_csr_misa_rmask)
|
||||
return input_ports + output_ports
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
insn_submodules = {}
|
||||
|
||||
m.submodules._lui = insn_submodules['lui'] = InsnLui(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._jal = insn_submodules['jal'] = InsnJal(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bne = insn_submodules['bne'] = InsnBne(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bge = insn_submodules['bge'] = InsnBge(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lb = insn_submodules['lb'] = InsnLb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lh = insn_submodules['lh'] = InsnLh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lw = insn_submodules['lw'] = InsnLw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sb = insn_submodules['sb'] = InsnSb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._sw = insn_submodules['sw'] = InsnSw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED)
|
||||
m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._xori = insn_submodules['xori'] = InsnXori(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._ori = insn_submodules['ori'] = InsnOri(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._add = insn_submodules['add'] = InsnAdd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sub = insn_submodules['sub'] = InsnSub(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sll = insn_submodules['sll'] = InsnSll(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._xor = insn_submodules['xor'] = InsnXor(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._sra = insn_submodules['sra'] = InsnSra(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA)
|
||||
m.submodules._lui = insn_submodules['lui'] = InsnLui(self.params)
|
||||
m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.params)
|
||||
m.submodules._jal = insn_submodules['jal'] = InsnJal(self.params)
|
||||
m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.params)
|
||||
m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.params)
|
||||
m.submodules._bne = insn_submodules['bne'] = InsnBne(self.params)
|
||||
m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.params)
|
||||
m.submodules._bge = insn_submodules['bge'] = InsnBge(self.params)
|
||||
m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.params)
|
||||
m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.params)
|
||||
m.submodules._lb = insn_submodules['lb'] = InsnLb(self.params)
|
||||
m.submodules._lh = insn_submodules['lh'] = InsnLh(self.params)
|
||||
m.submodules._lw = insn_submodules['lw'] = InsnLw(self.params)
|
||||
m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.params)
|
||||
m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.params)
|
||||
m.submodules._sb = insn_submodules['sb'] = InsnSb(self.params)
|
||||
m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.params)
|
||||
m.submodules._sw = insn_submodules['sw'] = InsnSw(self.params)
|
||||
m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.params)
|
||||
m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.params)
|
||||
m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.params)
|
||||
m.submodules._xori = insn_submodules['xori'] = InsnXori(self.params)
|
||||
m.submodules._ori = insn_submodules['ori'] = InsnOri(self.params)
|
||||
m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.params)
|
||||
m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.params)
|
||||
m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.params)
|
||||
m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.params)
|
||||
m.submodules._add = insn_submodules['add'] = InsnAdd(self.params)
|
||||
m.submodules._sub = insn_submodules['sub'] = InsnSub(self.params)
|
||||
m.submodules._sll = insn_submodules['sll'] = InsnSll(self.params)
|
||||
m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.params)
|
||||
m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.params)
|
||||
m.submodules._xor = insn_submodules['xor'] = InsnXor(self.params)
|
||||
m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.params)
|
||||
m.submodules._sra = insn_submodules['sra'] = InsnSra(self.params)
|
||||
m.submodules._or = insn_submodules['or'] = InsnOr(self.params)
|
||||
m.submodules._and = insn_submodules['and'] = InsnAnd(self.params)
|
||||
|
||||
for _, insn in insn_submodules.items():
|
||||
m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid)
|
||||
|
@ -150,7 +148,7 @@ class IsaRV32I(Elaboratable):
|
|||
m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata)
|
||||
m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata)
|
||||
m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata)
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata)
|
||||
|
||||
spec_valid = 0
|
||||
|
@ -208,7 +206,7 @@ class IsaRV32I(Elaboratable):
|
|||
spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata)
|
||||
m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata)
|
||||
|
||||
if self.RISCV_FORMAL_CSR_MISA:
|
||||
if self.params.csr_misa:
|
||||
spec_csr_misa_rmask = 0
|
||||
for _, insn in insn_submodules.items():
|
||||
spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask)
|
||||
|
|
|
@ -0,0 +1,4 @@
|
|||
from collections import namedtuple
|
||||
|
||||
RISCVFormalParameters = namedtuple('RISCVFormalParameters',
|
||||
['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem'])
|
Loading…
Reference in New Issue