M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Apply more PEP 8 guidelines, remove hacks and reduce code duplication #3

Merged
dsleung merged 4 commits from refactoring into master 2020-08-21 11:48:13 +08:00
Conversation 0 Commits 4 Files Changed 55 +2 -2
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit c6b9bb9a04 - Show all commits

4
README.md
View File

@ -4,14 +4,14 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
## Breakdown ## Breakdown
| Directory | Description | | File/Directory | Description |
| --- | --- | | --- | --- |
| `shell.nix` | [nix-shell](https://nixos.wiki/wiki/Development_environment_with_nix-shell) configuration file | | `shell.nix` | [nix-shell](https://nixos.wiki/wiki/Development_environment_with_nix-shell) configuration file |
| `rvfi` | RISC-V Formal Verification Framework (nMigen port) | | `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
| `rvfi/insns` | Supported RISC-V instructions and ISAs | | `rvfi/insns` | Supported RISC-V instructions and ISAs |
| `rvfi/checks` | Checks for RISC-V compliant cores | | `rvfi/checks` | Checks for RISC-V compliant cores |
| `rvfi/cores` | Cores currently tested against this port of riscv-formal | | `rvfi/cores` | Cores currently tested against this port of riscv-formal |
| `rvfi/cores/minerva` | Tests for the Minerva core | | `rvfi/cores/minerva/verify.py` | Verification tasks for the Minerva core |
## Running the Verification ## Running the Verification