M-Labs/riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Refactor supported instructions to improve code reuse #1

Merged
dsleung merged 84 commits from feature/refactor-insns into master 2020-08-06 09:47:30 +08:00
Conversation 0 Commits 84 Files Changed 56 +8 -8
2 changed files with 8 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit b583ab728f - Show all commits

8
insns/insn_UJ_type.py
View File

@ -23,12 +23,4 @@ class rvfi_insn_UJ_type(rvfi_insn_general):
m.d.comb += self.misa_ok.eq(1) m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0) m.d.comb += self.ialign16.eq(0)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m

8
insns/insn_jal.py
View File

@ -17,4 +17,12 @@ class rvfi_insn_jal(rvfi_insn_UJ_type):
m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m