M-Labs/riscv-formal-nmigen
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Refactor supported instructions to improve code reuse #1

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dsleung merged 84 commits from feature/refactor-insns into master 2020-08-06 09:47:30 +08:00
Conversation 0 Commits 84 Files Changed 56 +7 -7
2 changed files with 7 additions and 7 deletions
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7
insns/insn_I_type.py
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@ -27,11 +27,4 @@ class rvfi_insn_I_type(rvfi_insn_general):
m.d.comb += self.misa_ok.eq(1) m.d.comb += self.misa_ok.eq(1)
m.d.comb += self.ialign16.eq(0) m.d.comb += self.ialign16.eq(0)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m

7
insns/insn_jalr.py
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@ -18,4 +18,11 @@ class rvfi_insn_jalr(rvfi_insn_I_type):
m.d.comb += self.spec_pc_wdata.eq(next_pc) m.d.comb += self.spec_pc_wdata.eq(next_pc)
m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
# default assignments
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m