Commit Graph

368 Commits

Author SHA1 Message Date
Donald Sebastian Leung 978a620cc6 Limit no. of parallel processes to prevent thrashing 2020-09-21 13:45:36 +08:00
Donald Sebastian Leung c1a4617d74 Use m-labs nmigen repo 2020-09-21 11:30:48 +08:00
Donald Sebastian Leung 425bc49784 Parallelize all verification tasks for Minerva 2020-09-18 15:59:59 +08:00
Donald Sebastian Leung b0a914b48e Parallelize instruction verification tasks 2020-09-18 13:23:17 +08:00
Donald Sebastian Leung 283d8531e0 Update README 2020-09-17 17:06:55 +08:00
Donald Sebastian Leung c4cbc4bfea Explicitly define reset value in cycle signal for uniqueness check 2020-09-17 13:25:52 +08:00
Donald Sebastian Leung 32388adce0 Make liveness checks pass 2020-09-17 13:22:52 +08:00
Donald Sebastian Leung b38f19411a Make uniqueness checks pass 2020-09-17 13:08:04 +08:00
Donald Sebastian Leung e50d35ead5 Remove "Known issues" section in README 2020-09-16 17:12:40 +08:00
Donald Sebastian Leung a6b072efcf Fix parser error: invalid slice for memory-related instruction checks 2020-09-16 12:30:14 +08:00
Donald Sebastian Leung ee19bc49e7 Add bounded fairness constraints for liveness check 2020-09-15 17:12:58 +08:00
Donald Sebastian Leung e3b124f4eb Fix minor bug in SRL instruction specification 2020-09-15 16:35:05 +08:00
Donald Sebastian Leung c4daa89a88 Fix minor bug in JAL instruction specification 2020-09-15 16:12:34 +08:00
Donald Sebastian Leung 0f4a2a76bd Tweak parameters for Minerva verification tasks 2020-09-15 15:44:02 +08:00
Donald Sebastian Leung a9f1431959 Record failing instructions in individual instruction checks 2020-09-07 15:43:39 +08:00
Donald Sebastian Leung d84852e368 Replace unconditional pass and OOM issue with assertion failure 2020-09-07 12:32:14 +08:00
Donald Sebastian Leung d25785c4b4 Update README.md to reflect support for 64-bit ISAs 2020-08-28 12:33:14 +08:00
Donald Sebastian Leung b3acff2bf3 Update README.md 2020-08-28 12:30:39 +08:00
Donald Sebastian Leung e117fad73d Add RV64M Standard Extension 2020-08-28 12:20:56 +08:00
Donald Sebastian Leung 9b4644e905 Add REMUW instruction 2020-08-28 12:04:51 +08:00
Donald Sebastian Leung 64964655ff Add REMW instruction 2020-08-28 12:01:00 +08:00
Donald Sebastian Leung f1a5da1a34 Add DIVUW instruction 2020-08-28 11:55:11 +08:00
Donald Sebastian Leung b9f96a8ad0 Add DIVW instruction 2020-08-28 11:52:09 +08:00
Donald Sebastian Leung 1eab79538a Add MULW instruction 2020-08-28 11:45:45 +08:00
Donald Sebastian Leung 8fa2a33ecf Add RV64M R-Type Instruction 2020-08-28 11:37:54 +08:00
Donald Sebastian Leung 5d17b917b4 Update README.md 2020-08-27 16:25:54 +08:00
Donald Sebastian Leung fe5e73b6cb Add RV64I Base ISA 2020-08-27 16:21:53 +08:00
Donald Sebastian Leung e7066b8c89 Add SRAW instruction 2020-08-27 16:04:00 +08:00
Donald Sebastian Leung d188b9cdac Add SRLW instruction 2020-08-27 15:56:36 +08:00
Donald Sebastian Leung b60b590fe1 Add SLLW instruction 2020-08-27 15:54:01 +08:00
Donald Sebastian Leung 956be6570d Add SUBW instruction 2020-08-27 15:50:30 +08:00
Donald Sebastian Leung 2055f5159b Add ADDW instruction 2020-08-27 15:48:11 +08:00
Donald Sebastian Leung 6e4ecdcee0 Add RV64I R-Type Instruction 2020-08-27 15:39:09 +08:00
Donald Sebastian Leung cf295596ef Update README.md 2020-08-27 13:53:49 +08:00
Donald Sebastian Leung ade3d46b5b Add SRAIW instruction 2020-08-27 13:52:20 +08:00
Donald Sebastian Leung 94c19ed7f7 Add SRLIW instruction 2020-08-27 13:42:38 +08:00
Donald Sebastian Leung d837f6f8f6 Add SLLIW instruction 2020-08-27 13:39:11 +08:00
Donald Sebastian Leung 2790cb1f4c Add RV64I I-Type Instruction (Shift Variation) 2020-08-27 13:28:29 +08:00
Donald Sebastian Leung a15e57e12e Update README.md 2020-08-27 13:12:23 +08:00
Donald Sebastian Leung 3a332c5c1d Add ADDIW instruction 2020-08-27 13:11:23 +08:00
Donald Sebastian Leung dae95900b6 Update README.md 2020-08-27 12:54:28 +08:00
Donald Sebastian Leung 0954ee7fa9 Add SD instruction 2020-08-27 12:53:07 +08:00
Donald Sebastian Leung 472e0a70f8 Update README.md 2020-08-27 12:30:57 +08:00
Donald Sebastian Leung 94da2671dc Add LD instruction 2020-08-27 12:28:19 +08:00
Donald Sebastian Leung bd76a47a52 Add LWU instruction 2020-08-27 12:25:19 +08:00
Donald Sebastian Leung 92e34efe0d Add RV64I I-Type Instruction (Load Variation) 2020-08-27 12:20:17 +08:00
Donald Sebastian Leung 0af1f20423 Add RV64I I-Type Instruction 2020-08-27 11:46:04 +08:00
Donald Sebastian Leung fe835e272d Replace RV32I with RV32M for Minerva verification tasks 2020-08-27 10:48:35 +08:00
Donald Sebastian Leung 1ea25a4886 Add RV32M Standard Extension 2020-08-27 10:32:49 +08:00
Donald Sebastian Leung 3f3ec597a1 Update README.md 2020-08-26 17:21:27 +08:00