From eebb39ee27c85e69f31fdf24f50b8bf03360f21e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:15:09 +0800 Subject: [PATCH] Add S-type instruction format --- insns/insn_S.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 insns/insn_S.py diff --git a/insns/insn_S.py b/insns/insn_S.py new file mode 100644 index 0000000..b757fbf --- /dev/null +++ b/insns/insn_S.py @@ -0,0 +1,32 @@ +from insn import * +class rvfi_insn_S(rvfi_insn): + def __init__(self): + super(rvfi_insn_S, self).__init__() + self.insn_padding = Signal(32) + self.insn_imm = Signal(32) + self.insn_rs2 = Signal(5) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_S, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_S, self).elaborate(platform) + + # S-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) + m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rd_addr.eq(0) + m.d.comb += self.spec_rd_wdata.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + + return m