From edadb8da476c06fe6057ff8d5b3605d542bedee8 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Tue, 11 Aug 2020 16:37:42 +0800
Subject: [PATCH] Add RV32I SB-Type Instruction Format

---
 insns/InsnRV32ISBType.py | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 insns/InsnRV32ISBType.py

diff --git a/insns/InsnRV32ISBType.py b/insns/InsnRV32ISBType.py
new file mode 100644
index 0000000..dd19387
--- /dev/null
+++ b/insns/InsnRV32ISBType.py
@@ -0,0 +1,31 @@
+from Insn import *
+
+"""
+RV32I SB-Type Instruction
+"""
+
+class InsnRV32ISBType(Insn):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct3):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+        self.funct3 = funct3
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1))
+
+        if self.RISCV_FORMAL_CSR_MISA:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(4)
+            m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+            if self.RISCV_FORMAL_COMPRESSED:
+                m.d.comb += self.ialign16.eq(1)
+            else:
+                m.d.comb += self.ialign16.eq(0)
+
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b1100011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+
+        return m