From ecba1dc3e7e9eef703c61ace9b7eb25a59bd5e1f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 16:07:15 +0800 Subject: [PATCH] Add JALR instruction --- insns/insn_jalr.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 insns/insn_jalr.py diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py new file mode 100644 index 0000000..9ea4736 --- /dev/null +++ b/insns/insn_jalr.py @@ -0,0 +1,20 @@ +from insn_I import * + +class rvfi_insn_jalr(rvfi_insn_I): + def __init__(self): + super(rvfi_insn_jalr, self).__init__() + def ports(self): + return super(rvfi_insn_jalr, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_jalr, self).elaborate(platform) + + next_pc = Signal(32) + m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~1) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m