From e6c6f0462e72bbb34c0c055649cae87a5fb49d9c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 30 Jul 2020 13:48:01 +0800 Subject: [PATCH] Add I-type instruction format --- insns/insn_I_type.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 insns/insn_I_type.py diff --git a/insns/insn_I_type.py b/insns/insn_I_type.py new file mode 100644 index 0000000..1ecf805 --- /dev/null +++ b/insns/insn_I_type.py @@ -0,0 +1,37 @@ +from insn_general import * + +class rvfi_insn_I_type(rvfi_insn_general): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + super(rvfi_insn_I_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) + self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) + self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + self.ialign16 = Signal(1) + def ports(self): + return super(rvfi_insn_I_type, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I_type, self).elaborate(platform) + + # I-type instruction format + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + m.d.comb += self.ialign16.eq(0) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m