From e3f0727e9c5284018f9152cf3846934a6ed25999 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Fri, 31 Jul 2020 16:31:25 +0800
Subject: [PATCH] Add LBU instruction
---
insns/insn_lbu.py | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 insns/insn_lbu.py
diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py
new file mode 100644
index 0000000..3961c99
--- /dev/null
+++ b/insns/insn_lbu.py
@@ -0,0 +1,25 @@
+from insn_I import *
+
+class rvfi_insn_lbu(rvfi_insn_I):
+ def __init__(self):
+ super(rvfi_insn_lbu, self).__init__()
+ def ports(self):
+ return super(rvfi_insn_lbu, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_lbu, self).elaborate(platform)
+
+ # LBU instruction
+ addr = Signal(32)
+ m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ result = Signal(8)
+ m.d.comb += result.eq(self.rvfi_mem_rdata)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b0000011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+ m.d.comb += self.spec_mem_addr.eq(addr)
+ m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1)
+ m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+ return m