From e1bbf567c22c9083febf0c44d5816881a33796c2 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Tue, 4 Aug 2020 16:57:43 +0800
Subject: [PATCH] Add MUL instruction
---
insns/insn_mul.py | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 insns/insn_mul.py
diff --git a/insns/insn_mul.py b/insns/insn_mul.py
new file mode 100644
index 0000000..5f250b1
--- /dev/null
+++ b/insns/insn_mul.py
@@ -0,0 +1,23 @@
+from insn_R import *
+
+class rvfi_insn_mul(rvfi_insn_R):
+ def __init__(self):
+ super(rvfi_insn_mul, self).__init__()
+ def ports(self):
+ return super(rvfi_insn_mul, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_mul, self).elaborate(platform)
+
+ # MUL instruction
+ altops_bitmask = Signal(32)
+ m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e)
+ result = Signal(32)
+ m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b0110011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+ m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+ return m