diff --git a/rvfi/insns/README.md b/rvfi/insns/README.md index 48dd648..00e3768 100644 --- a/rvfi/insns/README.md +++ b/rvfi/insns/README.md @@ -89,14 +89,14 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `IsaRV32I`: RV32I Base ISA -## Core-specific constants +## Core-specific parameters -The following core-specific constants are currently supported: +The following core-specific parameters are currently supported: -| Constant | Description | Valid value(s) | Supported by instruction(s) | Supported by ISA(s) | -| --- | --- | --- | --- | --- | -| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | -| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | -| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | RV32I | -| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | RV32I | -| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW | RV32I | +| Constant | Description | Valid value(s) | +| --- | --- | --- | +| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | +| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | +| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | +| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | +| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | diff --git a/rvfi/insns/insn.py b/rvfi/insns/insn.py index a47a129..fe7f510 100644 --- a/rvfi/insns/insn.py +++ b/rvfi/insns/insn.py @@ -47,6 +47,7 @@ class Insn(Elaboratable): self.insn_opcode = Signal(7) self.misa_ok = Signal(1) self.ialign16 = Signal(1) + def ports(self): input_ports = [ self.rvfi_valid, @@ -74,6 +75,7 @@ class Insn(Elaboratable): if self.params.csr_misa: output_ports.append(self.spec_csr_misa_rmask) return input_ports + output_ports + def elaborate(self, platform): m = Module() diff --git a/rvfi/insns/insn_add.py b/rvfi/insns/insn_add.py index abac425..54162fc 100644 --- a/rvfi/insns/insn_add.py +++ b/rvfi/insns/insn_add.py @@ -7,6 +7,7 @@ ADD instruction class InsnAdd(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b000, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_addi.py b/rvfi/insns/insn_addi.py index b6c3f95..58aaf52 100644 --- a/rvfi/insns/insn_addi.py +++ b/rvfi/insns/insn_addi.py @@ -7,6 +7,7 @@ ADDI instruction class InsnAddi(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b000) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_and.py b/rvfi/insns/insn_and.py index 07deb1f..e85402e 100644 --- a/rvfi/insns/insn_and.py +++ b/rvfi/insns/insn_and.py @@ -7,6 +7,7 @@ AND instruction class InsnAnd(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b111, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_andi.py b/rvfi/insns/insn_andi.py index 4e7d1f5..cdc7473 100644 --- a/rvfi/insns/insn_andi.py +++ b/rvfi/insns/insn_andi.py @@ -7,6 +7,7 @@ ANDI instruction class InsnAndi(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b111) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_auipc.py b/rvfi/insns/insn_auipc.py index a5dcd0b..bd92a9d 100644 --- a/rvfi/insns/insn_auipc.py +++ b/rvfi/insns/insn_auipc.py @@ -7,6 +7,7 @@ AUIPC instruction class InsnAuipc(InsnRV32IUType): def __init__(self, params): super().__init__(params, 0b0010111) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_beq.py b/rvfi/insns/insn_beq.py index 5e5944c..04e3416 100644 --- a/rvfi/insns/insn_beq.py +++ b/rvfi/insns/insn_beq.py @@ -7,6 +7,7 @@ BEQ instruction class InsnBeq(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b000) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_bge.py b/rvfi/insns/insn_bge.py index 8f592df..a916d42 100644 --- a/rvfi/insns/insn_bge.py +++ b/rvfi/insns/insn_bge.py @@ -7,6 +7,7 @@ BGE instruction class InsnBge(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_bgeu.py b/rvfi/insns/insn_bgeu.py index 089900e..bfc1798 100644 --- a/rvfi/insns/insn_bgeu.py +++ b/rvfi/insns/insn_bgeu.py @@ -7,6 +7,7 @@ BGEU instruction class InsnBgeu(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b111) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_blt.py b/rvfi/insns/insn_blt.py index 4433e03..0e6c573 100644 --- a/rvfi/insns/insn_blt.py +++ b/rvfi/insns/insn_blt.py @@ -7,6 +7,7 @@ BLT instruction class InsnBlt(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b100) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_bltu.py b/rvfi/insns/insn_bltu.py index 0ec2ec4..bf395d6 100644 --- a/rvfi/insns/insn_bltu.py +++ b/rvfi/insns/insn_bltu.py @@ -7,6 +7,7 @@ BLTU instruction class InsnBltu(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b110) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_bne.py b/rvfi/insns/insn_bne.py index ddfdb59..c4b9964 100644 --- a/rvfi/insns/insn_bne.py +++ b/rvfi/insns/insn_bne.py @@ -7,6 +7,7 @@ BNE instruction class InsnBne(InsnRV32ISBType): def __init__(self, params): super().__init__(params, 0b001) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_lui.py b/rvfi/insns/insn_lui.py index 93cddd9..68689fc 100644 --- a/rvfi/insns/insn_lui.py +++ b/rvfi/insns/insn_lui.py @@ -7,6 +7,7 @@ LUI instruction class InsnLui(InsnRV32IUType): def __init__(self, params): super().__init__(params, 0b0110111) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_or.py b/rvfi/insns/insn_or.py index 61ececa..6f0970f 100644 --- a/rvfi/insns/insn_or.py +++ b/rvfi/insns/insn_or.py @@ -7,6 +7,7 @@ OR instruction class InsnOr(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b110, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_ori.py b/rvfi/insns/insn_ori.py index dab6bc4..a1ba9a6 100644 --- a/rvfi/insns/insn_ori.py +++ b/rvfi/insns/insn_ori.py @@ -7,6 +7,7 @@ ORI instruction class InsnOri(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b110) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_i_type_arith.py b/rvfi/insns/insn_rv32i_i_type_arith.py index 65806e5..c69989c 100644 --- a/rvfi/insns/insn_rv32i_i_type_arith.py +++ b/rvfi/insns/insn_rv32i_i_type_arith.py @@ -8,6 +8,7 @@ class InsnRV32IITypeArith(InsnRV32IIType): def __init__(self, params, funct3): super().__init__(params) self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_i_type_load.py b/rvfi/insns/insn_rv32i_i_type_load.py index a1820c5..3ef5e55 100644 --- a/rvfi/insns/insn_rv32i_i_type_load.py +++ b/rvfi/insns/insn_rv32i_i_type_load.py @@ -12,6 +12,7 @@ class InsnRV32IITypeLoad(InsnRV32IIType): self.is_signed = is_signed self.addr = Signal(self.params.xlen) self.result = Signal(8 * self.mask_shift) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_i_type_shift.py b/rvfi/insns/insn_rv32i_i_type_shift.py index 37bb303..d92d2c8 100644 --- a/rvfi/insns/insn_rv32i_i_type_shift.py +++ b/rvfi/insns/insn_rv32i_i_type_shift.py @@ -9,6 +9,7 @@ class InsnRV32IITypeShift(Insn): super().__init__(params) self.funct6 = funct6 self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_r_type.py b/rvfi/insns/insn_rv32i_r_type.py index c516f82..a901718 100644 --- a/rvfi/insns/insn_rv32i_r_type.py +++ b/rvfi/insns/insn_rv32i_r_type.py @@ -10,6 +10,7 @@ class InsnRV32IRType(Insn): self.funct7 = funct7 self.funct3 = funct3 self.opcode = opcode + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_s_type.py b/rvfi/insns/insn_rv32i_s_type.py index 6023237..6e4cf9d 100644 --- a/rvfi/insns/insn_rv32i_s_type.py +++ b/rvfi/insns/insn_rv32i_s_type.py @@ -10,6 +10,7 @@ class InsnRV32ISType(Insn): self.funct3 = funct3 self.mask_shift = mask_shift self.addr = Signal(self.params.xlen) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_sb_type.py b/rvfi/insns/insn_rv32i_sb_type.py index c368c15..b68e55e 100644 --- a/rvfi/insns/insn_rv32i_sb_type.py +++ b/rvfi/insns/insn_rv32i_sb_type.py @@ -8,6 +8,7 @@ class InsnRV32ISBType(Insn): def __init__(self, params, funct3): super().__init__(params) self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv32i_u_type.py b/rvfi/insns/insn_rv32i_u_type.py index e76daf5..4319a09 100644 --- a/rvfi/insns/insn_rv32i_u_type.py +++ b/rvfi/insns/insn_rv32i_u_type.py @@ -8,6 +8,7 @@ class InsnRV32IUType(Insn): def __init__(self, params, opcode): super().__init__(params) self.opcode = opcode + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sll.py b/rvfi/insns/insn_sll.py index c15f502..9263fe5 100644 --- a/rvfi/insns/insn_sll.py +++ b/rvfi/insns/insn_sll.py @@ -7,6 +7,7 @@ SLL instruction class InsnSll(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b001, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_slli.py b/rvfi/insns/insn_slli.py index 36a2712..1c8dede 100644 --- a/rvfi/insns/insn_slli.py +++ b/rvfi/insns/insn_slli.py @@ -7,6 +7,7 @@ SLLI instruction class InsnSlli(InsnRV32IITypeShift): def __init__(self, params): super().__init__(params, 0b000000, 0b001) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_slt.py b/rvfi/insns/insn_slt.py index 588295c..6504552 100644 --- a/rvfi/insns/insn_slt.py +++ b/rvfi/insns/insn_slt.py @@ -7,6 +7,7 @@ SLT instruction class InsnSlt(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b010, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_slti.py b/rvfi/insns/insn_slti.py index 6377914..a647058 100644 --- a/rvfi/insns/insn_slti.py +++ b/rvfi/insns/insn_slti.py @@ -7,6 +7,7 @@ SLTI instruction class InsnSlti(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b010) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sltiu.py b/rvfi/insns/insn_sltiu.py index 552b552..922bb96 100644 --- a/rvfi/insns/insn_sltiu.py +++ b/rvfi/insns/insn_sltiu.py @@ -7,6 +7,7 @@ SLTIU instruction class InsnSltiu(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sltu.py b/rvfi/insns/insn_sltu.py index 6e5c477..7644099 100644 --- a/rvfi/insns/insn_sltu.py +++ b/rvfi/insns/insn_sltu.py @@ -7,6 +7,7 @@ SLTU instruction class InsnSltu(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b011, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sra.py b/rvfi/insns/insn_sra.py index b96bbbb..6cbc76a 100644 --- a/rvfi/insns/insn_sra.py +++ b/rvfi/insns/insn_sra.py @@ -7,6 +7,7 @@ SRA instruction class InsnSra(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0100000, 0b101, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_srai.py b/rvfi/insns/insn_srai.py index 985f467..1e1f6a4 100644 --- a/rvfi/insns/insn_srai.py +++ b/rvfi/insns/insn_srai.py @@ -7,6 +7,7 @@ SRAI instruction class InsnSrai(InsnRV32IITypeShift): def __init__(self, params): super().__init__(params, 0b010000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_srl.py b/rvfi/insns/insn_srl.py index 6a2cc46..4f2d2f9 100644 --- a/rvfi/insns/insn_srl.py +++ b/rvfi/insns/insn_srl.py @@ -7,6 +7,7 @@ SRL instruction class InsnSrl(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b100, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_srli.py b/rvfi/insns/insn_srli.py index e36a907..372b05a 100644 --- a/rvfi/insns/insn_srli.py +++ b/rvfi/insns/insn_srli.py @@ -7,6 +7,7 @@ SRLI instruction class InsnSrli(InsnRV32IITypeShift): def __init__(self, params): super().__init__(params, 0b000000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sub.py b/rvfi/insns/insn_sub.py index a056975..247fed9 100644 --- a/rvfi/insns/insn_sub.py +++ b/rvfi/insns/insn_sub.py @@ -7,6 +7,7 @@ SUB instruction class InsnSub(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0100000, 0b000, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_xor.py b/rvfi/insns/insn_xor.py index 9107836..d5c907d 100644 --- a/rvfi/insns/insn_xor.py +++ b/rvfi/insns/insn_xor.py @@ -7,6 +7,7 @@ XOR instruction class InsnXor(InsnRV32IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b100, 0b0110011) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_xori.py b/rvfi/insns/insn_xori.py index d89bceb..58d13bd 100644 --- a/rvfi/insns/insn_xori.py +++ b/rvfi/insns/insn_xori.py @@ -7,6 +7,7 @@ XORI instruction class InsnXori(InsnRV32IITypeArith): def __init__(self, params): super().__init__(params, 0b100) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/isa_rv32i.py b/rvfi/insns/isa_rv32i.py index 8b317ea..e98b076 100644 --- a/rvfi/insns/isa_rv32i.py +++ b/rvfi/insns/isa_rv32i.py @@ -41,38 +41,35 @@ RV32I Base ISA """ class IsaRV32I(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM): - # Core-specific constants - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA - self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED - self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM + def __init__(self, params): + # Core-specific parameters + self.params = params # Input ports self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - if self.RISCV_FORMAL_CSR_MISA: - self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_insn = Signal(self.params.ilen) + self.rvfi_pc_rdata = Signal(self.params.xlen) + self.rvfi_rs1_rdata = Signal(self.params.xlen) + self.rvfi_rs2_rdata = Signal(self.params.xlen) + self.rvfi_mem_rdata = Signal(self.params.xlen) + if self.params.csr_misa: + self.rvfi_csr_misa_rdata = Signal(self.params.xlen) # Output ports - if self.RISCV_FORMAL_CSR_MISA: - self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) + if self.params.csr_misa: + self.spec_csr_misa_rmask = Signal(self.params.xlen) self.spec_valid = Signal(1) self.spec_trap = Signal(1) self.spec_rs1_addr = Signal(5) self.spec_rs2_addr = Signal(5) self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_rd_wdata = Signal(self.params.xlen) + self.spec_pc_wdata = Signal(self.params.xlen) + self.spec_mem_addr = Signal(self.params.xlen) + self.spec_mem_rmask = Signal(int(self.params.xlen // 8)) + self.spec_mem_wmask = Signal(int(self.params.xlen // 8)) + self.spec_mem_wdata = Signal(self.params.xlen) + def ports(self): input_ports = [ self.rvfi_valid, @@ -82,7 +79,7 @@ class IsaRV32I(Elaboratable): self.rvfi_rs2_rdata, self.rvfi_mem_rdata ] - if self.RISCV_FORMAL_CSR_MISA: + if self.params.csr_misa: input_ports.append(self.rvfi_csr_misa_rdata) output_ports = [ self.spec_valid, @@ -97,51 +94,52 @@ class IsaRV32I(Elaboratable): self.spec_mem_wmask, self.spec_mem_wdata ] - if self.RISCV_FORMAL_CSR_MISA: + if self.params.csr_misa: output_ports.append(self.spec_csr_misa_rmask) return input_ports + output_ports + def elaborate(self, platform): m = Module() insn_submodules = {} - m.submodules._lui = insn_submodules['lui'] = InsnLui(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._jal = insn_submodules['jal'] = InsnJal(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._bne = insn_submodules['bne'] = InsnBne(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._bge = insn_submodules['bge'] = InsnBge(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._lb = insn_submodules['lb'] = InsnLb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._lh = insn_submodules['lh'] = InsnLh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._lw = insn_submodules['lw'] = InsnLw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._sb = insn_submodules['sb'] = InsnSb(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._sw = insn_submodules['sw'] = InsnSw(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA, self.RISCV_FORMAL_COMPRESSED) - m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._xori = insn_submodules['xori'] = InsnXori(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._ori = insn_submodules['ori'] = InsnOri(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._add = insn_submodules['add'] = InsnAdd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._sub = insn_submodules['sub'] = InsnSub(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._sll = insn_submodules['sll'] = InsnSll(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._xor = insn_submodules['xor'] = InsnXor(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._sra = insn_submodules['sra'] = InsnSra(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._or = insn_submodules['or'] = InsnOr(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) - m.submodules._and = insn_submodules['and'] = InsnAnd(self.RISCV_FORMAL_ILEN, self.RISCV_FORMAL_XLEN, self.RISCV_FORMAL_CSR_MISA) + m.submodules._lui = insn_submodules['lui'] = InsnLui(self.params) + m.submodules._auipc = insn_submodules['auipc'] = InsnAuipc(self.params) + m.submodules._jal = insn_submodules['jal'] = InsnJal(self.params) + m.submodules._jalr = insn_submodules['jalr'] = InsnJalr(self.params) + m.submodules._beq = insn_submodules['beq'] = InsnBeq(self.params) + m.submodules._bne = insn_submodules['bne'] = InsnBne(self.params) + m.submodules._blt = insn_submodules['blt'] = InsnBlt(self.params) + m.submodules._bge = insn_submodules['bge'] = InsnBge(self.params) + m.submodules._bltu = insn_submodules['bltu'] = InsnBltu(self.params) + m.submodules._bgeu = insn_submodules['bgeu'] = InsnBgeu(self.params) + m.submodules._lb = insn_submodules['lb'] = InsnLb(self.params) + m.submodules._lh = insn_submodules['lh'] = InsnLh(self.params) + m.submodules._lw = insn_submodules['lw'] = InsnLw(self.params) + m.submodules._lbu = insn_submodules['lbu'] = InsnLbu(self.params) + m.submodules._lhu = insn_submodules['lhu'] = InsnLhu(self.params) + m.submodules._sb = insn_submodules['sb'] = InsnSb(self.params) + m.submodules._sh = insn_submodules['Sh'] = InsnSh(self.params) + m.submodules._sw = insn_submodules['sw'] = InsnSw(self.params) + m.submodules._addi = insn_submodules['addi'] = InsnAddi(self.params) + m.submodules._slti = insn_submodules['slti'] = InsnSlti(self.params) + m.submodules._sltiu = insn_submodules['sltiu'] = InsnSltiu(self.params) + m.submodules._xori = insn_submodules['xori'] = InsnXori(self.params) + m.submodules._ori = insn_submodules['ori'] = InsnOri(self.params) + m.submodules._andi = insn_submodules['andi'] = InsnAndi(self.params) + m.submodules._slli = insn_submodules['slli'] = InsnSlli(self.params) + m.submodules._srli = insn_submodules['srli'] = InsnSrli(self.params) + m.submodules._srai = insn_submodules['srai'] = InsnSrai(self.params) + m.submodules._add = insn_submodules['add'] = InsnAdd(self.params) + m.submodules._sub = insn_submodules['sub'] = InsnSub(self.params) + m.submodules._sll = insn_submodules['sll'] = InsnSll(self.params) + m.submodules._slt = insn_submodules['slt'] = InsnSlt(self.params) + m.submodules._sltu = insn_submodules['sltu'] = InsnSltu(self.params) + m.submodules._xor = insn_submodules['xor'] = InsnXor(self.params) + m.submodules._srl = insn_submodules['srl'] = InsnSrl(self.params) + m.submodules._sra = insn_submodules['sra'] = InsnSra(self.params) + m.submodules._or = insn_submodules['or'] = InsnOr(self.params) + m.submodules._and = insn_submodules['and'] = InsnAnd(self.params) for _, insn in insn_submodules.items(): m.d.comb += insn.rvfi_valid.eq(self.rvfi_valid) @@ -150,7 +148,7 @@ class IsaRV32I(Elaboratable): m.d.comb += insn.rvfi_rs1_rdata.eq(self.rvfi_rs1_rdata) m.d.comb += insn.rvfi_rs2_rdata.eq(self.rvfi_rs2_rdata) m.d.comb += insn.rvfi_mem_rdata.eq(self.rvfi_mem_rdata) - if self.RISCV_FORMAL_CSR_MISA: + if self.params.csr_misa: m.d.comb += insn.rvfi_csr_misa_rdata.eq(self.rvfi_csr_misa_rdata) spec_valid = 0 @@ -208,7 +206,7 @@ class IsaRV32I(Elaboratable): spec_mem_wdata = Mux(insn.spec_valid, insn.spec_mem_wdata, spec_mem_wdata) m.d.comb += self.spec_mem_wdata.eq(spec_mem_wdata) - if self.RISCV_FORMAL_CSR_MISA: + if self.params.csr_misa: spec_csr_misa_rmask = 0 for _, insn in insn_submodules.items(): spec_csr_misa_rmask = Mux(insn.spec_valid, insn.spec_csr_misa_rmask, spec_csr_misa_rmask)