From dd17606902f48eaac7accaabc4fde26c2057b4eb Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Wed, 26 Aug 2020 15:48:55 +0800
Subject: [PATCH] Add RV32M R-Type Instruction
---
rvfi/insns/insn_rv32m_r_type.py | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 rvfi/insns/insn_rv32m_r_type.py
diff --git a/rvfi/insns/insn_rv32m_r_type.py b/rvfi/insns/insn_rv32m_r_type.py
new file mode 100644
index 0000000..14567ed
--- /dev/null
+++ b/rvfi/insns/insn_rv32m_r_type.py
@@ -0,0 +1,26 @@
+from .insn import *
+
+"""
+RV32M R-Type Instruction
+"""
+
+class InsnRV32MRType(Insn):
+ def __init__(self, params, funct3):
+ super().__init__(params)
+ self.funct3 = funct3
+ def elaborate(self, platform):
+ m = super().elaborate(platform)
+
+ if self.params.csr_misa:
+ m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0x1000) == 0x1000)
+ m.d.comb += self.spec_csr_misa_rmask.eq(0x1000)
+ else:
+ m.d.comb += self.misa_ok.eq(1)
+
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000001) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0110011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+ return m