diff --git a/insns/insn_lw.py b/insns/insn_lw.py
new file mode 100644
index 0000000..5e956e9
--- /dev/null
+++ b/insns/insn_lw.py
@@ -0,0 +1,25 @@
+from insn_I import *
+
+class rvfi_insn_lw(rvfi_insn_I):
+    def __init__(self):
+        super(rvfi_insn_lw, self).__init__()
+    def ports(self):
+        return super(rvfi_insn_lw, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_lw, self).elaborate(platform)
+
+        # LW instruction
+        addr = Signal(32)
+        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+        result = Signal(32)
+        m.d.comb += result.eq(self.rvfi_mem_rdata)
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b010) & (self.insn_opcode == 0b0000011))
+        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_mem_addr.eq(addr)
+        m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1)
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
+        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+        return m