From d33dc1b137cd93d32e11147e2912043be220f3f1 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:29:54 +0800 Subject: [PATCH] Add SLT instruction --- insns/InsnSlt.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSlt.py diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py new file mode 100644 index 0000000..7ba4b9e --- /dev/null +++ b/insns/InsnSlt.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSlt(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) + def elaborate(self, platform): + m = super(InsnSlt, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), 0)) + + return m