From d06daac123ece13904faa52b0fb82220b8c82489 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 7 Aug 2020 15:51:21 +0800 Subject: [PATCH] Add SRA instruction --- insns/InsnSra.py | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 insns/InsnSra.py diff --git a/insns/InsnSra.py b/insns/InsnSra.py new file mode 100644 index 0000000..bccf74b --- /dev/null +++ b/insns/InsnSra.py @@ -0,0 +1,11 @@ +from InsnRV32IRType import * + +class InsnSra(InsnRV32IRType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) + def elaborate(self, platform): + m = super(InsnSra, self).elaborate(platform) + + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) + + return m