From ccc1bd098b32ea58ac4dbb72458536505cf71838 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Fri, 7 Aug 2020 13:54:00 +0800
Subject: [PATCH] Add ADD instruction
---
insns/InsnAdd.py | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 insns/InsnAdd.py
diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py
new file mode 100644
index 0000000..16d2de3
--- /dev/null
+++ b/insns/InsnAdd.py
@@ -0,0 +1,11 @@
+from InsnRV32IRType import *
+
+class InsnAdd(InsnRV32IRType):
+ def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+ super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011)
+ def elaborate(self, platform):
+ m = super(InsnAdd, self).elaborate(platform)
+
+ m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.rvfi_rs2_rdata, 0))
+
+ return m