From c82dcfb570ef734418160ea96892196a3f5033d8 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 11 Aug 2020 16:54:16 +0800 Subject: [PATCH] Add BGE instruction --- insns/InsnBge.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 insns/InsnBge.py diff --git a/insns/InsnBge.py b/insns/InsnBge.py new file mode 100644 index 0000000..2158e79 --- /dev/null +++ b/insns/InsnBge.py @@ -0,0 +1,18 @@ +from InsnRV32ISBType import * + +""" +BGE instruction +""" + +class InsnBge(InsnRV32ISBType): + def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b101) + def elaborate(self, platform): + m = super().elaborate(platform) + + next_pc = Signal(self.RISCV_FORMAL_XLEN) + m.d.comb += next_pc.eq(Mux(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata), self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m