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riscv-formal-nmigen
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Modify MUL instruction to use alternative operations

This commit is contained in:
Donald Sebastian Leung 2020-07-24 13:13:03 +08:00
parent dec39cb11d
commit c72205d433
1 changed files with 3 additions and 1 deletions
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4
insns/insn_mul.py
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@ -67,8 +67,10 @@ class rvfi_insn_mul(Elaboratable):
m.d.comb += misa_ok.eq(1) m.d.comb += misa_ok.eq(1)
# MUL instruction # MUL instruction
altops_bitmask = Signal(64)
m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e)
result = Signal(self.RISCV_FORMAL_XLEN) result = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += result.eq(self.rvfi_rs1_rdata * self.rvfi_rs2_rdata) m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask)
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011))
m.d.comb += self.spec_rs1_addr.eq(insn_rs1) m.d.comb += self.spec_rs1_addr.eq(insn_rs1)
m.d.comb += self.spec_rs2_addr.eq(insn_rs2) m.d.comb += self.spec_rs2_addr.eq(insn_rs2)