Explicitly define reset value in cycle signal for uniqueness check

2020-09-17 13:25:52 +08:00 · 2020-09-17 13:25:52 +08:00 · c4cbc4bfea
parent 32388adce0
commit c4cbc4bfea
1 changed files with 1 additions and 1 deletions
--- a/rvfi/cores/minerva/verify.py
+++ b/rvfi/cores/minerva/verify.py
@ -555,7 +555,7 @@ class UniqueSpec(Elaboratable):
        m.d.comb += cpu.dbus.ack.eq(AnySeq(1))
        m.d.comb += cpu.dbus.err.eq(0)
        
-        cycle = Signal(8)
+        cycle = Signal(8, reset=0)
        with m.If(cycle != 0xFF):
            m.d.sync += cycle.eq(cycle + 1)
        m.d.comb += unique_spec.reset.eq(cycle < 1)