From c17ccdf897b78836b8a64c7ef01b87780489f43f Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 10:28:01 +0800 Subject: [PATCH] Add BEQ instruction --- insns/insn_beq.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_beq.py diff --git a/insns/insn_beq.py b/insns/insn_beq.py new file mode 100644 index 0000000..466e2a5 --- /dev/null +++ b/insns/insn_beq.py @@ -0,0 +1,21 @@ +from insn_SB import * + +class rvfi_insn_beq(rvfi_insn_SB): + def __init__(self): + super(rvfi_insn_beq, self).__init__() + def ports(self): + return super(rvfi_insn_beq, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_beq, self).elaborate(platform) + + cond = Signal(1) + m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) + next_pc = Signal(32) + m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_pc_wdata.eq(next_pc) + m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) + + return m