diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py
new file mode 100644
index 0000000..9bc6e6b
--- /dev/null
+++ b/insns/InsnRV32IITypeLoad.py
@@ -0,0 +1,48 @@
+from InsnRV32IIType import *
+
+"""
+RV32I I-Type Instruction (Load Variation)
+"""
+
+class InsnRV32IITypeLoad(InsnRV32IIType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+        self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
+        self.funct3 = funct3
+        self.mask_shift = mask_shift
+        self.is_signed = is_signed
+        self.addr = Signal(self.RISCV_FORMAL_XLEN)
+        self.result = Signal(8 * self.mask_shift)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        if self.RISCV_FORMAL_CSR_MISA:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+
+        if self.RISCV_FORMAL_ALIGNED_MEM:
+            m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+            m.d.comb += self.result.eq(self.rvfi_mem_rdata >> (8 * (self.addr - self.spec_mem_addr)))
+            m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
+            m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+            m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+            m.d.comb += self.spec_mem_addr.eq(self.addr & ~(int(self.RISCV_FORMAL_XLEN // 8) - 1))
+            m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (self.addr - self.spec_mem_addr))
+            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0))
+            m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+            m.d.comb += self.spec_trap.eq(((self.addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
+        else:
+            m.d.comb += self.addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+            m.d.comb += self.result.eq(self.rvfi_mem_rdata)
+            m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
+            m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+            m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+            m.d.comb += self.spec_mem_addr.eq(self.addr)
+            m.d.comb += self.spec_mem_rmask.eq((1 << self.mask_shift) - 1)
+            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.result) if self.is_signed else self.result, 0))
+            m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+            m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+        return m