diff --git a/insns/InsnJal.py b/insns/InsnJal.py
new file mode 100644
index 0000000..68ed094
--- /dev/null
+++ b/insns/InsnJal.py
@@ -0,0 +1,32 @@
+from Insn import *
+
+"""
+JAL instruction
+"""
+
+class InsnJal(Insn):
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
+
+        if self.RISCV_FORMAL_CSR_MISA:
+            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+            m.d.comb += self.spec_csr_misa_rmask.eq(4)
+            m.d.comb += self.ialign16.eq((self.rvfi_csr_misa_rdata & 4) != 0)
+        else:
+            m.d.comb += self.misa_ok.eq(1)
+            if self.RISCV_FORMAL_COMPRESSED:
+                m.d.comb += self.ialign16.eq(1)
+            else:
+                m.d.comb += self.ialign16.eq(0)
+
+        next_pc = Signal(self.RISCV_FORMAL_XLEN)
+        m.d.comb += next_pc.eq(self.rvfi_rs1_rdata + self.insn_imm)
+        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111))
+        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0))
+        m.d.comb += self.spec_pc_wdata.eq(next_pc)
+        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
+
+        return m