From badd480a45a2be7405db5c9314151877c4006551 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 23 Jul 2020 12:42:59 +0800 Subject: [PATCH] Prepare generator script for RV32I ISA --- insns/isa_rv32i.py | 56 ++++++++++++++++++++++++++++++++++++++ insns/isa_rv32i_gen.py | 62 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) create mode 100644 insns/isa_rv32i.py create mode 100644 insns/isa_rv32i_gen.py diff --git a/insns/isa_rv32i.py b/insns/isa_rv32i.py new file mode 100644 index 0000000..8fc3b9a --- /dev/null +++ b/insns/isa_rv32i.py @@ -0,0 +1,56 @@ +# Generated by isa_rv32i_gen.py +from nmigen import * + +class rvfi_isa_rv32i(Elaboratable): + def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): + self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN + self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN + self.rvfi_valid = Signal(1) + self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) + self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) + self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) + + self.spec_valid = Signal(1) + self.spec_trap = Signal(1) + self.spec_rs1_addr = Signal(5) + self.spec_rs2_addr = Signal(5) + self.spec_rd_addr = Signal(5) + self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) + self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) + self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) + def ports(self): + input_ports = [ + self.rvfi_valid, + self.rvfi_insn, + self.rvfi_pc_rdata, + self.rvfi_rs1_rdata, + self.rvfi_rs2_rdata, + self.rvfi_mem_rdata + ] + output_ports = [ + self.spec_valid, + self.spec_trap, + self.spec_rs1_addr, + self.spec_rs2_addr, + self.spec_rd_addr, + self.spec_rd_wdata, + self.spec_pc_wdata, + self.spec_mem_addr, + self.spec_mem_rmask, + self.spec_mem_wmask, + self.spec_mem_wdata + ] + def elaborate(self, platform): + m = Module() + + + return m + +test = rvfi_isa_rv32i() +test.ports() +test.elaborate(platform=None) diff --git a/insns/isa_rv32i_gen.py b/insns/isa_rv32i_gen.py new file mode 100644 index 0000000..03b2ef3 --- /dev/null +++ b/insns/isa_rv32i_gen.py @@ -0,0 +1,62 @@ +with open('isa_rv32i.py', 'w') as isa_rv32i: + def fprint(strng): + print(strng, file=isa_rv32i) + fprint("# Generated by isa_rv32i_gen.py") + fprint("from nmigen import *") + fprint("") + fprint("class rvfi_isa_rv32i(Elaboratable):") + fprint(" def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):") + fprint(" self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN") + fprint(" self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN") + fprint(" self.rvfi_valid = Signal(1)") + fprint(" self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)") + fprint(" self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint("") + fprint(" self.spec_valid = Signal(1)") + fprint(" self.spec_trap = Signal(1)") + fprint(" self.spec_rs1_addr = Signal(5)") + fprint(" self.spec_rs2_addr = Signal(5)") + fprint(" self.spec_rd_addr = Signal(5)") + fprint(" self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") + fprint(" self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))") + fprint(" self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)") + fprint(" def ports(self):") + fprint(" input_ports = [") + fprint(" self.rvfi_valid,") + fprint(" self.rvfi_insn,") + fprint(" self.rvfi_pc_rdata,") + fprint(" self.rvfi_rs1_rdata,") + fprint(" self.rvfi_rs2_rdata,") + fprint(" self.rvfi_mem_rdata") + fprint(" ]") + fprint(" output_ports = [") + fprint(" self.spec_valid,") + fprint(" self.spec_trap,") + fprint(" self.spec_rs1_addr,") + fprint(" self.spec_rs2_addr,") + fprint(" self.spec_rd_addr,") + fprint(" self.spec_rd_wdata,") + fprint(" self.spec_pc_wdata,") + fprint(" self.spec_mem_addr,") + fprint(" self.spec_mem_rmask,") + fprint(" self.spec_mem_wmask,") + fprint(" self.spec_mem_wdata") + fprint(" ]") + fprint(" def elaborate(self, platform):") + fprint(" m = Module()") + fprint("") + # TODO + fprint("") + fprint(" return m") + + # For debugging purposes only + fprint("") + fprint("test = rvfi_isa_rv32i()") + fprint("test.ports()") + fprint("test.elaborate(platform=None)")