diff --git a/rvfi/insns/insn_divw.py b/rvfi/insns/insn_divw.py
new file mode 100644
index 0000000..5976b4c
--- /dev/null
+++ b/rvfi/insns/insn_divw.py
@@ -0,0 +1,20 @@
+from .insn_rv64m_r_type import *
+
+"""
+DIVW instruction
+"""
+
+class InsnDivw(InsnRV64MRType):
+    def __init__(self, params):
+        super.__init__(params, 0b100)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        result = Signal(32)
+        if self.params.altops:
+            m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0x29bbf66f7f8529ec)
+        else:
+            m.d.comb += result.eq(Mux(self.rvfi_rs2_rdata[:32] == 0, 2 ** 32 - 1, Mux((self.rvfi_rs1_rdata == (1 << 31)) & (self.rvfi_rs2_rdata == 2 ** 32 - 1), 1 << 31, Value.as_signed(self.rvfi_rs1_rdata[:32]) // Value.as_signed(self.rvfi_rs2_rdata[:32]))))
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
+
+        return m