diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py
index 137d8be..b5a6ade 100644
--- a/insns/insn_UJ_type.py
+++ b/insns/insn_UJ_type.py
@@ -23,12 +23,4 @@ class rvfi_insn_UJ_type(rvfi_insn_general):
         m.d.comb += self.misa_ok.eq(1)
         m.d.comb += self.ialign16.eq(0)
 
-        # default assignments
-        m.d.comb += self.spec_rs1_addr.eq(0)
-        m.d.comb += self.spec_rs2_addr.eq(0)
-        m.d.comb += self.spec_mem_addr.eq(0)
-        m.d.comb += self.spec_mem_rmask.eq(0)
-        m.d.comb += self.spec_mem_wmask.eq(0)
-        m.d.comb += self.spec_mem_wdata.eq(0)
-
         return m
diff --git a/insns/insn_jal.py b/insns/insn_jal.py
index 1eaab3c..baf1c35 100644
--- a/insns/insn_jal.py
+++ b/insns/insn_jal.py
@@ -17,4 +17,12 @@ class rvfi_insn_jal(rvfi_insn_UJ_type):
         m.d.comb += self.spec_pc_wdata.eq(next_pc)
         m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)
 
+        # default assignments
+        m.d.comb += self.spec_rs1_addr.eq(0)
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
         return m