diff --git a/README.md b/README.md index e50ac92..f65c0e9 100644 --- a/README.md +++ b/README.md @@ -31,7 +31,7 @@ This should run in the order of a few minutes. ## Scope -Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits. +The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but yet to be fully tested. Support for compressed instructions may be added in the future as time permits. ## Known Issues diff --git a/rvfi/insns/README.md b/rvfi/insns/README.md index 5382933..c538a19 100644 --- a/rvfi/insns/README.md +++ b/rvfi/insns/README.md @@ -109,12 +109,19 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnSrlw`: SRLW instruction - `InsnSraw`: SRAW instruction - `InsnSd`: SD instruction + - `InsnRV64MRType`: RV64M R-Type Instruction + - `InsnMulw`: MULW instruction + - `InsnDivw`: DIVW instruction + - `InsnDivuw`: DIVUW instruction + - `InsnRemw`: REMW instruction + - `InsnRemuw`: REMUW instruction ### ISAs - `IsaRV32I`: RV32I Base ISA - `IsaRV32M`: RV32M Standard Extension - `IsaRV64I`: RV64I Base ISA +- `IsaRV64M`: RV64M Standard Extension ## Core-specific parameters diff --git a/rvfi/insns/insn_addw.py b/rvfi/insns/insn_addw.py index 115af96..acda9af 100644 --- a/rvfi/insns/insn_addw.py +++ b/rvfi/insns/insn_addw.py @@ -7,6 +7,7 @@ ADDW instruction class InsnAddw(InsnRV64IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b000) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_divuw.py b/rvfi/insns/insn_divuw.py index f8b3346..fb2bb7a 100644 --- a/rvfi/insns/insn_divuw.py +++ b/rvfi/insns/insn_divuw.py @@ -7,6 +7,7 @@ DIVUW instruction class InsnDivuw(InsnRV64MRType): def __init__(self, params): super().__init__(params, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_divw.py b/rvfi/insns/insn_divw.py index e2ceac4..b937db1 100644 --- a/rvfi/insns/insn_divw.py +++ b/rvfi/insns/insn_divw.py @@ -7,6 +7,7 @@ DIVW instruction class InsnDivw(InsnRV64MRType): def __init__(self, params): super().__init__(params, 0b100) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_mulw.py b/rvfi/insns/insn_mulw.py index 3313d4b..de2b4a6 100644 --- a/rvfi/insns/insn_mulw.py +++ b/rvfi/insns/insn_mulw.py @@ -7,6 +7,7 @@ MULW instruction class InsnMulw(InsnRV64MRType): def __init__(self, params): super().__init__(params, 0b000) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_remuw.py b/rvfi/insns/insn_remuw.py index 7f9f23d..43c2ee3 100644 --- a/rvfi/insns/insn_remuw.py +++ b/rvfi/insns/insn_remuw.py @@ -7,6 +7,7 @@ REMUW instruction class InsnRemuw(InsnRV64MRType): def __init__(self, params): super().__init__(params, 0b111) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_remw.py b/rvfi/insns/insn_remw.py index 18995c4..b017250 100644 --- a/rvfi/insns/insn_remw.py +++ b/rvfi/insns/insn_remw.py @@ -7,6 +7,7 @@ REMW instruction class InsnRemw(InsnRV64MRType): def __init__(self, params): super().__init__(params, 0b110) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv64i_i_type_load.py b/rvfi/insns/insn_rv64i_i_type_load.py index 8cd3bd7..d322ced 100644 --- a/rvfi/insns/insn_rv64i_i_type_load.py +++ b/rvfi/insns/insn_rv64i_i_type_load.py @@ -10,6 +10,7 @@ class InsnRV64IITypeLoad(InsnRV64IIType): self.mask_shift = mask_shift self.funct3 = funct3 self.is_signed = is_signed + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv64i_i_type_shift.py b/rvfi/insns/insn_rv64i_i_type_shift.py index f39a168..167eb62 100644 --- a/rvfi/insns/insn_rv64i_i_type_shift.py +++ b/rvfi/insns/insn_rv64i_i_type_shift.py @@ -9,6 +9,7 @@ class InsnRV64IITypeShift(InsnRV64IIType): super().__init__(params) self.funct6 = funct6 self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv64i_r_type.py b/rvfi/insns/insn_rv64i_r_type.py index 5a596b6..f2f4485 100644 --- a/rvfi/insns/insn_rv64i_r_type.py +++ b/rvfi/insns/insn_rv64i_r_type.py @@ -9,6 +9,7 @@ class InsnRV64IRType(Insn): super().__init__(params) self.funct7 = funct7 self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_rv64m_r_type.py b/rvfi/insns/insn_rv64m_r_type.py index abf2f74..bdf5ddf 100644 --- a/rvfi/insns/insn_rv64m_r_type.py +++ b/rvfi/insns/insn_rv64m_r_type.py @@ -8,6 +8,7 @@ class InsnRV64MRType(Insn): def __init__(self, params, funct3): super().__init__(params) self.funct3 = funct3 + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_slliw.py b/rvfi/insns/insn_slliw.py index 42a4b62..3eb8896 100644 --- a/rvfi/insns/insn_slliw.py +++ b/rvfi/insns/insn_slliw.py @@ -7,6 +7,7 @@ SLLIW instruction class InsnSlliw(InsnRV64IITypeShift): def __init__(self, params): super().__init__(params, 0b000000, 0b001) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sllw.py b/rvfi/insns/insn_sllw.py index eb5c794..904b389 100644 --- a/rvfi/insns/insn_sllw.py +++ b/rvfi/insns/insn_sllw.py @@ -7,6 +7,7 @@ SLLW instruction class InsnSllw(InsnRV64IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b001) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sraiw.py b/rvfi/insns/insn_sraiw.py index 8e2b635..e84b772 100644 --- a/rvfi/insns/insn_sraiw.py +++ b/rvfi/insns/insn_sraiw.py @@ -7,6 +7,7 @@ SRAIW instruction class InsnSraiw(InsnRV64IITypeShift): def __init__(self, params): super().__init__(params, 0b010000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_sraw.py b/rvfi/insns/insn_sraw.py index 55228db..51ac38f 100644 --- a/rvfi/insns/insn_sraw.py +++ b/rvfi/insns/insn_sraw.py @@ -7,6 +7,7 @@ SRAW instruction class InsnSraw(InsnRV64IRType): def __init__(self, params): super().__init__(params, 0b0100000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_srliw.py b/rvfi/insns/insn_srliw.py index 05f41b6..e4a58e8 100644 --- a/rvfi/insns/insn_srliw.py +++ b/rvfi/insns/insn_srliw.py @@ -7,6 +7,7 @@ SRLIW instruction class InsnSrliw(InsnRV64IITypeShift): def __init__(self, params): super().__init__(params, 0b000000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_srlw.py b/rvfi/insns/insn_srlw.py index ebf845f..0c1abd9 100644 --- a/rvfi/insns/insn_srlw.py +++ b/rvfi/insns/insn_srlw.py @@ -7,6 +7,7 @@ SRLW instruction class InsnSrlw(InsnRV64IRType): def __init__(self, params): super().__init__(params, 0b0000000, 0b101) + def elaborate(self, platform): m = super().elaborate(platform) diff --git a/rvfi/insns/insn_subw.py b/rvfi/insns/insn_subw.py index d2ad511..6444bb2 100644 --- a/rvfi/insns/insn_subw.py +++ b/rvfi/insns/insn_subw.py @@ -7,6 +7,7 @@ SUBW instruction class InsnSubw(InsnRV64IRType): def __init__(self, params): super().__init__(params, 0b0100000, 0b000) + def elaborate(self, platform): m = super().elaborate(platform)