diff --git a/insns/InsnRV32IITypeLoad.py b/insns/InsnRV32IITypeLoad.py
index 8dba77c..d1d790b 100644
--- a/insns/InsnRV32IITypeLoad.py
+++ b/insns/InsnRV32IITypeLoad.py
@@ -5,8 +5,8 @@ RV32I I-Type Instruction (Load Variation)
 """
 
 class InsnRV32IITypeLoad(InsnRV32IIType):
-    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
-        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED)
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM, funct3, mask_shift, is_signed):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
         self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
         self.funct3 = funct3
         self.mask_shift = mask_shift