Parallelize instruction verification tasks
parent
283d8531e0
commit
b0a914b48e
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@ -27,7 +27,7 @@ This should run the tests (cache, multiplier, divider) provided by Minerva itsel
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$ python -m rvfi.cores.minerva.verify
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$ python -m rvfi.cores.minerva.verify
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```
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```
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This should run in the order of a few hours.
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This should complete within 2 hours.
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## Scope
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## Scope
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@ -38,7 +38,6 @@ The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM
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In no particular order:
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In no particular order:
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- Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only `20`)
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- Combine individual instruction checks into single ISA check (currently, doing so takes forever even when depth is set to only `20`)
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- Parallelize execution of verification tasks to reduce the total time required to run all verification tasks on a multi-core system
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## License
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## License
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@ -53,6 +53,7 @@ from ...insns.insn_divu import *
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from ...insns.insn_rem import *
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from ...insns.insn_rem import *
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from ...insns.insn_remu import *
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from ...insns.insn_remu import *
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from collections import namedtuple
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from collections import namedtuple
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from multiprocessing import Process
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RISCVFormalParameters = namedtuple('RISCVFormalParameters',
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RISCVFormalParameters = namedtuple('RISCVFormalParameters',
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['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem', 'altops'])
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['ilen', 'xlen', 'csr_misa', 'compressed', 'aligned_mem', 'altops'])
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@ -124,141 +125,64 @@ class InsnSpec(Elaboratable):
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class InsnTestCase(FHDLTestCase):
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class InsnTestCase(FHDLTestCase):
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def verify(self):
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def verify(self):
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print("- Verifying LUI instruction ...")
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def verify_insn(insn_spec, spec_name):
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self.assertFormal(InsnSpec(InsnLui), mode="cover", depth=20)
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self.assertFormal(InsnSpec(insn_spec), mode="cover", depth=20, spec_name=spec_name)
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self.assertFormal(InsnSpec(InsnLui), mode="bmc", depth=20)
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self.assertFormal(InsnSpec(insn_spec), mode="bmc", depth=20, spec_name=spec_name)
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print("- Verifying AUIPC instruction ...")
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print("%s PASS" % spec_name)
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self.assertFormal(InsnSpec(InsnAuipc), mode="cover", depth=20)
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insns = [
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self.assertFormal(InsnSpec(InsnAuipc), mode="bmc", depth=20)
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(InsnLui, "verify_lui"),
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print("- Verifying JAL instruction ...")
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(InsnAuipc, "verify_auipc"),
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self.assertFormal(InsnSpec(InsnJal), mode="cover", depth=20)
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(InsnJal, "verify_jal"),
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self.assertFormal(InsnSpec(InsnJal), mode="bmc", depth=20)
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(InsnJalr, "verify_jalr"),
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print("- Verifying JALR instruction ...")
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(InsnBeq, "verify_beq"),
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self.assertFormal(InsnSpec(InsnJalr), mode="cover", depth=20)
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(InsnBne, "verify_bne"),
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self.assertFormal(InsnSpec(InsnJalr), mode="bmc", depth=20)
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(InsnBlt, "verify_blt"),
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print("- Verifying BEQ instruction ...")
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(InsnBge, "verify_bge"),
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self.assertFormal(InsnSpec(InsnBeq), mode="cover", depth=20)
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(InsnBltu, "verify_bltu"),
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self.assertFormal(InsnSpec(InsnBeq), mode="bmc", depth=20)
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(InsnBgeu, "verify_bgeu"),
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print("- Verifying BNE instruction ...")
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(InsnLb, "verify_lb"),
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self.assertFormal(InsnSpec(InsnBne), mode="cover", depth=20)
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(InsnLh, "verify_lh"),
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self.assertFormal(InsnSpec(InsnBne), mode="bmc", depth=20)
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(InsnLw, "verify_lw"),
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print("- Verifying BLT instruction ...")
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(InsnLbu, "verify_lbu"),
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self.assertFormal(InsnSpec(InsnBlt), mode="cover", depth=20)
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(InsnLhu, "verify_lhu"),
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self.assertFormal(InsnSpec(InsnBlt), mode="bmc", depth=20)
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(InsnSb, "verify_sb"),
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print("- Verifying BGE instruction ...")
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(InsnSh, "verify_sh"),
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self.assertFormal(InsnSpec(InsnBge), mode="cover", depth=20)
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(InsnSw, "verify_sw"),
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self.assertFormal(InsnSpec(InsnBge), mode="bmc", depth=20)
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(InsnAddi, "verify_addi"),
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print("- Verifying BLTU instruction ...")
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(InsnSlti, "verify_slti"),
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self.assertFormal(InsnSpec(InsnBltu), mode="cover", depth=20)
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(InsnSltiu, "verify_sltiu"),
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self.assertFormal(InsnSpec(InsnBltu), mode="bmc", depth=20)
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(InsnXori, "verify_xori"),
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print("- Verifying BGEU instruction ...")
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(InsnOri, "verify_ori"),
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self.assertFormal(InsnSpec(InsnBgeu), mode="cover", depth=20)
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(InsnAndi, "verify_andi"),
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self.assertFormal(InsnSpec(InsnBgeu), mode="bmc", depth=20)
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(InsnSlli, "verify_slli"),
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print("- Verifying LB instruction ...")
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(InsnSrli, "verify_srli"),
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self.assertFormal(InsnSpec(InsnLb), mode="cover", depth=20)
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(InsnSrai, "verify_srai"),
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self.assertFormal(InsnSpec(InsnLb), mode="bmc", depth=20)
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(InsnAdd, "verify_add"),
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print("- Verifying LH instruction ...")
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(InsnSub, "verify_sub"),
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self.assertFormal(InsnSpec(InsnLh), mode="cover", depth=20)
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(InsnSll, "verify_sll"),
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self.assertFormal(InsnSpec(InsnLh), mode="bmc", depth=20)
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(InsnSlt, "verify_slt"),
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print("- Verifying LW instruction ...")
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(InsnSltu, "verify_sltu"),
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self.assertFormal(InsnSpec(InsnLw), mode="cover", depth=20)
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(InsnXor, "verify_xor"),
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self.assertFormal(InsnSpec(InsnLw), mode="bmc", depth=20)
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(InsnSrl, "verify_srl"),
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print("- Verifying LBU instruction ...")
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(InsnSra, "verify_sra"),
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self.assertFormal(InsnSpec(InsnLbu), mode="cover", depth=20)
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(InsnOr, "verify_or"),
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self.assertFormal(InsnSpec(InsnLbu), mode="bmc", depth=20)
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(InsnAnd, "verify_and"),
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print("- Verifying LHU instruction ...")
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(InsnMul, "verify_mul"),
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self.assertFormal(InsnSpec(InsnLhu), mode="cover", depth=20)
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(InsnMulh, "verify_mulh"),
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self.assertFormal(InsnSpec(InsnLhu), mode="bmc", depth=20)
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(InsnMulhsu, "verify_mulhsu"),
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print("- Verifying SB instruction ...")
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(InsnMulhu, "verify_mulhu"),
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self.assertFormal(InsnSpec(InsnSb), mode="cover", depth=20)
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(InsnDiv, "verify_div"),
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self.assertFormal(InsnSpec(InsnSb), mode="bmc", depth=20)
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(InsnDivu, "verify_divu"),
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print("- Verifying SH instruction ...")
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(InsnRem, "verify_rem"),
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self.assertFormal(InsnSpec(InsnSh), mode="cover", depth=20)
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(InsnRemu, "verify_remu")
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self.assertFormal(InsnSpec(InsnSh), mode="bmc", depth=20)
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]
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print("- Verifying SW instruction ...")
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ps = []
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self.assertFormal(InsnSpec(InsnSw), mode="cover", depth=20)
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for insn_spec, spec_name in insns:
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self.assertFormal(InsnSpec(InsnSw), mode="bmc", depth=20)
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p = Process(target=verify_insn, args=(insn_spec,spec_name))
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print("- Verifying ADDI instruction ...")
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ps.append(p)
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self.assertFormal(InsnSpec(InsnAddi), mode="cover", depth=20)
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p.start()
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self.assertFormal(InsnSpec(InsnAddi), mode="bmc", depth=20)
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for p in ps:
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print("- Verifying SLTI instruction ...")
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p.join()
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self.assertFormal(InsnSpec(InsnSlti), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSlti), mode="bmc", depth=20)
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print("- Verifying SLTIU instruction ...")
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self.assertFormal(InsnSpec(InsnSltiu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSltiu), mode="bmc", depth=20)
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print("- Verifying XORI instruction ...")
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self.assertFormal(InsnSpec(InsnXori), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnXori), mode="bmc", depth=20)
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print("- Verifying ORI instruction ...")
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self.assertFormal(InsnSpec(InsnOri), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnOri), mode="bmc", depth=20)
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print("- Verifying ANDI instruction ...")
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self.assertFormal(InsnSpec(InsnAndi), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnAndi), mode="bmc", depth=20)
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print("- Verifying SLLI instruction ...")
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self.assertFormal(InsnSpec(InsnSlli), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSlli), mode="bmc", depth=20)
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print("- Verifying SRLI instruction ...")
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self.assertFormal(InsnSpec(InsnSrli), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSrli), mode="bmc", depth=20)
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print("- Verifying SRAI instruction ...")
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self.assertFormal(InsnSpec(InsnSrai), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSrai), mode="bmc", depth=20)
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print("- Verifying ADD instruction ...")
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self.assertFormal(InsnSpec(InsnAdd), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnAdd), mode="bmc", depth=20)
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print("- Verifying SUB instruction ...")
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self.assertFormal(InsnSpec(InsnSub), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSub), mode="bmc", depth=20)
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print("- Verifying SLL instruction ...")
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self.assertFormal(InsnSpec(InsnSll), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSll), mode="bmc", depth=20)
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print("- Verifying SLT instruction ...")
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self.assertFormal(InsnSpec(InsnSlt), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSlt), mode="bmc", depth=20)
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print("- Verifying SLTU instruction ...")
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self.assertFormal(InsnSpec(InsnSltu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSltu), mode="bmc", depth=20)
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print("- Verifying XOR instruction ...")
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self.assertFormal(InsnSpec(InsnXor), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnXor), mode="bmc", depth=20)
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print("- Verifying SRL instruction ...")
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self.assertFormal(InsnSpec(InsnSrl), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSrl), mode="bmc", depth=20)
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print("- Verifying SRA instruction ...")
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self.assertFormal(InsnSpec(InsnSra), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnSra), mode="bmc", depth=20)
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print("- Verifying OR instruction ...")
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self.assertFormal(InsnSpec(InsnOr), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnOr), mode="bmc", depth=20)
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print("- Verifying AND instruction ...")
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self.assertFormal(InsnSpec(InsnAnd), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnAnd), mode="bmc", depth=20)
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print("- Verifying MUL instruction ...")
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self.assertFormal(InsnSpec(InsnMul), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnMul), mode="bmc", depth=20)
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print("- Verifying MULH instruction ...")
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self.assertFormal(InsnSpec(InsnMulh), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnMulh), mode="bmc", depth=20)
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print("- Verifying MULHSU instruction ...")
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self.assertFormal(InsnSpec(InsnMulhsu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnMulhsu), mode="bmc", depth=20)
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print("- Verifying MULHU instruction ...")
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self.assertFormal(InsnSpec(InsnMulhu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnMulhu), mode="bmc", depth=20)
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print("- Verifying DIV instruction ...")
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self.assertFormal(InsnSpec(InsnDiv), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnDiv), mode="bmc", depth=20)
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print("- Verifying DIVU instruction ...")
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self.assertFormal(InsnSpec(InsnDivu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnDivu), mode="bmc", depth=20)
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print("- Verifying REM instruction ...")
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self.assertFormal(InsnSpec(InsnRem), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnRem), mode="bmc", depth=20)
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print("- Verifying REMU instruction ...")
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self.assertFormal(InsnSpec(InsnRemu), mode="cover", depth=20)
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self.assertFormal(InsnSpec(InsnRemu), mode="bmc", depth=20)
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class PcFwdSpec(Elaboratable):
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class PcFwdSpec(Elaboratable):
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def elaborate(self, platform):
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def elaborate(self, platform):
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@ -2,10 +2,10 @@ let
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pkgs = import <nixpkgs> { };
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pkgs = import <nixpkgs> { };
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nmigen-latest = pkgs.python3Packages.nmigen.overrideAttrs(oa: {
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nmigen-latest = pkgs.python3Packages.nmigen.overrideAttrs(oa: {
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src = pkgs.fetchFromGitHub {
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src = pkgs.fetchFromGitHub {
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owner = "m-labs";
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owner = "DonaldKellett";
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repo = "nmigen";
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repo = "nmigen";
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rev = "1ad6e3207f02e913407867dddddb8f50fad0ced4";
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rev = "03726c7e3f307f27626bcc7dffe75abe17b2a390";
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sha256 = "14vvw1lcfmcf3374wpn3sslgvgcfg18rkbs8x45vycqag6a5zy0b";
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sha256 = "1b0rjbb6is6nzbcnxrwh5iv4k9xcac0ijq5kp47wdg9rhbnaa5w0";
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};
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};
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});
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});
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minerva-latest = pkgs.python3Packages.buildPythonPackage {
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minerva-latest = pkgs.python3Packages.buildPythonPackage {
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