From aa9967e83d329945e35b546251277fdd9fb9904b Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Fri, 31 Jul 2020 11:17:58 +0800 Subject: [PATCH] Start over in insns/ --- insns/insn_I_type.py | 30 --------------- insns/insn_SB_type.py | 30 --------------- insns/insn_UJ_type.py | 26 ------------- insns/insn_U_type.py | 24 ------------ insns/insn_add.py | 86 ------------------------------------------ insns/insn_addi.py | 84 ----------------------------------------- insns/insn_and.py | 86 ------------------------------------------ insns/insn_andi.py | 84 ----------------------------------------- insns/insn_auipc.py | 26 ------------- insns/insn_beq.py | 30 --------------- insns/insn_bge.py | 30 --------------- insns/insn_bgeu.py | 30 --------------- insns/insn_blt.py | 30 --------------- insns/insn_bltu.py | 30 --------------- insns/insn_bne.py | 30 --------------- insns/insn_div.py | 88 ------------------------------------------- insns/insn_divu.py | 88 ------------------------------------------- insns/insn_general.py | 50 ------------------------ insns/insn_jal.py | 28 -------------- insns/insn_jalr.py | 28 -------------- insns/insn_lb.py | 86 ------------------------------------------ insns/insn_lbu.py | 86 ------------------------------------------ insns/insn_lh.py | 86 ------------------------------------------ insns/insn_lhu.py | 86 ------------------------------------------ insns/insn_lui.py | 26 ------------- insns/insn_lw.py | 86 ------------------------------------------ insns/insn_mul.py | 88 ------------------------------------------- insns/insn_mulh.py | 88 ------------------------------------------- insns/insn_mulhsu.py | 88 ------------------------------------------- insns/insn_mulhu.py | 88 ------------------------------------------- insns/insn_or.py | 86 ------------------------------------------ insns/insn_ori.py | 84 ----------------------------------------- insns/insn_rem.py | 88 ------------------------------------------- insns/insn_remu.py | 88 ------------------------------------------- insns/insn_sb.py | 84 ----------------------------------------- insns/insn_sh.py | 84 ----------------------------------------- insns/insn_sll.py | 88 ------------------------------------------- insns/insn_slli.py | 86 ------------------------------------------ insns/insn_slt.py | 86 ------------------------------------------ insns/insn_slti.py | 84 ----------------------------------------- insns/insn_sltiu.py | 84 ----------------------------------------- insns/insn_sltu.py | 86 ------------------------------------------ insns/insn_sra.py | 88 ------------------------------------------- insns/insn_srai.py | 86 ------------------------------------------ insns/insn_srl.py | 88 ------------------------------------------- insns/insn_srli.py | 86 ------------------------------------------ insns/insn_sub.py | 86 ------------------------------------------ insns/insn_sw.py | 84 ----------------------------------------- insns/insn_xor.py | 86 ------------------------------------------ insns/insn_xori.py | 84 ----------------------------------------- 50 files changed, 3462 deletions(-) delete mode 100644 insns/insn_I_type.py delete mode 100644 insns/insn_SB_type.py delete mode 100644 insns/insn_UJ_type.py delete mode 100644 insns/insn_U_type.py delete mode 100644 insns/insn_add.py delete mode 100644 insns/insn_addi.py delete mode 100644 insns/insn_and.py delete mode 100644 insns/insn_andi.py delete mode 100644 insns/insn_auipc.py delete mode 100644 insns/insn_beq.py delete mode 100644 insns/insn_bge.py delete mode 100644 insns/insn_bgeu.py delete mode 100644 insns/insn_blt.py delete mode 100644 insns/insn_bltu.py delete mode 100644 insns/insn_bne.py delete mode 100644 insns/insn_div.py delete mode 100644 insns/insn_divu.py delete mode 100644 insns/insn_general.py delete mode 100644 insns/insn_jal.py delete mode 100644 insns/insn_jalr.py delete mode 100644 insns/insn_lb.py delete mode 100644 insns/insn_lbu.py delete mode 100644 insns/insn_lh.py delete mode 100644 insns/insn_lhu.py delete mode 100644 insns/insn_lui.py delete mode 100644 insns/insn_lw.py delete mode 100644 insns/insn_mul.py delete mode 100644 insns/insn_mulh.py delete mode 100644 insns/insn_mulhsu.py delete mode 100644 insns/insn_mulhu.py delete mode 100644 insns/insn_or.py delete mode 100644 insns/insn_ori.py delete mode 100644 insns/insn_rem.py delete mode 100644 insns/insn_remu.py delete mode 100644 insns/insn_sb.py delete mode 100644 insns/insn_sh.py delete mode 100644 insns/insn_sll.py delete mode 100644 insns/insn_slli.py delete mode 100644 insns/insn_slt.py delete mode 100644 insns/insn_slti.py delete mode 100644 insns/insn_sltiu.py delete mode 100644 insns/insn_sltu.py delete mode 100644 insns/insn_sra.py delete mode 100644 insns/insn_srai.py delete mode 100644 insns/insn_srl.py delete mode 100644 insns/insn_srli.py delete mode 100644 insns/insn_sub.py delete mode 100644 insns/insn_sw.py delete mode 100644 insns/insn_xor.py delete mode 100644 insns/insn_xori.py diff --git a/insns/insn_I_type.py b/insns/insn_I_type.py deleted file mode 100644 index 51a71d4..0000000 --- a/insns/insn_I_type.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_general import * - -class rvfi_insn_I_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_I_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_I_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_I_type, self).elaborate(platform) - - # I-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_SB_type.py b/insns/insn_SB_type.py deleted file mode 100644 index e92ef6a..0000000 --- a/insns/insn_SB_type.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_general import * - -class rvfi_insn_SB_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_SB_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rs2 = Signal(5) - self.insn_rs1 = Signal(5) - self.insn_funct3 = Signal(3) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_SB_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_SB_type, self).elaborate(platform) - - # SB-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[8:12], self.rvfi_insn[25:31], self.rvfi_insn[7], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rs2.eq(self.rvfi_insn[20:25]) - m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) - m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py deleted file mode 100644 index b5a6ade..0000000 --- a/insns/insn_UJ_type.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_general import * - -class rvfi_insn_UJ_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_UJ_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - self.ialign16 = Signal(1) - def ports(self): - return super(rvfi_insn_UJ_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_UJ_type, self).elaborate(platform) - - # UJ-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - m.d.comb += self.ialign16.eq(0) - - return m diff --git a/insns/insn_U_type.py b/insns/insn_U_type.py deleted file mode 100644 index adc1257..0000000 --- a/insns/insn_U_type.py +++ /dev/null @@ -1,24 +0,0 @@ -from insn_general import * - -class rvfi_insn_U_type(rvfi_insn_general): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_U_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - self.insn_padding = Signal(self.RISCV_FORMAL_ILEN) - self.insn_imm = Signal(self.RISCV_FORMAL_XLEN) - self.insn_rd = Signal(5) - self.insn_opcode = Signal(7) - self.misa_ok = Signal(1) - def ports(self): - return super(rvfi_insn_U_type, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_U_type, self).elaborate(platform) - - # U-type instruction format - m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) - m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12)) - m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) - m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) - - m.d.comb += self.misa_ok.eq(1) - - return m diff --git a/insns/insn_add.py b/insns/insn_add.py deleted file mode 100644 index d995dff..0000000 --- a/insns/insn_add.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_add(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ADD instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_addi.py b/insns/insn_addi.py deleted file mode 100644 index 634279d..0000000 --- a/insns/insn_addi.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_addi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ADDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_and.py b/insns/insn_and.py deleted file mode 100644 index e27275b..0000000 --- a/insns/insn_and.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_and(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # AND instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_andi.py b/insns/insn_andi.py deleted file mode 100644 index 5f3a91d..0000000 --- a/insns/insn_andi.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_andi(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ANDI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata & insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b111) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_auipc.py b/insns/insn_auipc.py deleted file mode 100644 index 425a7db..0000000 --- a/insns/insn_auipc.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_U_type import * - -class rvfi_insn_auipc(rvfi_insn_U_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_auipc, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_auipc, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_auipc, self).elaborate(platform) - - # AUIPC instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0010111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_beq.py b/insns/insn_beq.py deleted file mode 100644 index 48aa0c6..0000000 --- a/insns/insn_beq.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_beq(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_beq, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_beq, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_beq, self).elaborate(platform) - - # BEQ instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata == self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bge.py b/insns/insn_bge.py deleted file mode 100644 index 62bee30..0000000 --- a/insns/insn_bge.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bge(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bge, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bge, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bge, self).elaborate(platform) - - # BGE instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) >= Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bgeu.py b/insns/insn_bgeu.py deleted file mode 100644 index 64b95e7..0000000 --- a/insns/insn_bgeu.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bgeu(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bgeu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bgeu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bgeu, self).elaborate(platform) - - # BGEU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata >= self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_blt.py b/insns/insn_blt.py deleted file mode 100644 index 35d8121..0000000 --- a/insns/insn_blt.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_blt(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_blt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_blt, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_blt, self).elaborate(platform) - - # BLT instruction - cond = Signal(1) - m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bltu.py b/insns/insn_bltu.py deleted file mode 100644 index 36b6652..0000000 --- a/insns/insn_bltu.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bltu(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bltu, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bltu, self).elaborate(platform) - - # BLTU instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b110) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_bne.py b/insns/insn_bne.py deleted file mode 100644 index cb7551b..0000000 --- a/insns/insn_bne.py +++ /dev/null @@ -1,30 +0,0 @@ -from insn_SB_type import * - -class rvfi_insn_bne(rvfi_insn_SB_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_bne, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_bne, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_bne, self).elaborate(platform) - - # BNE instruction - cond = Signal(1) - m.d.comb += cond.eq(self.rvfi_rs1_rdata != self.rvfi_rs2_rdata) - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b1100011)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_div.py b/insns/insn_div.py deleted file mode 100644 index 5d71a32..0000000 --- a/insns/insn_div.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_div(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # DIV instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x29bbf66f7f8529ec) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_divu.py b/insns/insn_divu.py deleted file mode 100644 index c5677f6..0000000 --- a/insns/insn_divu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_divu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # DIVU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x8c629acb10e8fd70) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_general.py b/insns/insn_general.py deleted file mode 100644 index c649196..0000000 --- a/insns/insn_general.py +++ /dev/null @@ -1,50 +0,0 @@ -from nmigen import * - -class rvfi_insn_general(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - return m diff --git a/insns/insn_jal.py b/insns/insn_jal.py deleted file mode 100644 index baf1c35..0000000 --- a/insns/insn_jal.py +++ /dev/null @@ -1,28 +0,0 @@ -from insn_UJ_type import * - -class rvfi_insn_jal(rvfi_insn_UJ_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_jal, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_jal, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jal, self).elaborate(platform) - - # JAL instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq(self.rvfi_pc_rdata + self.insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b1101111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_jalr.py b/insns/insn_jalr.py deleted file mode 100644 index e4f3540..0000000 --- a/insns/insn_jalr.py +++ /dev/null @@ -1,28 +0,0 @@ -from insn_I_type import * - -class rvfi_insn_jalr(rvfi_insn_I_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_jalr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_jalr, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_jalr, self).elaborate(platform) - - # JALR instruction - next_pc = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += next_pc.eq((self.rvfi_rs1_rdata + self.insn_imm) & ~Const(1, shape=self.RISCV_FORMAL_XLEN)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b000) & (self.insn_opcode == 0b1100111)) - m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_pc_rdata + 4, 0)) - m.d.comb += self.spec_pc_wdata.eq(next_pc) - m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lb.py b/insns/insn_lb.py deleted file mode 100644 index 10d2561..0000000 --- a/insns/insn_lb.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b000) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lbu.py b/insns/insn_lbu.py deleted file mode 100644 index db836ad..0000000 --- a/insns/insn_lbu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lbu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LBU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(8) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b100) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 1) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lh.py b/insns/insn_lh.py deleted file mode 100644 index c6a00fc..0000000 --- a/insns/insn_lh.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b001) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lhu.py b/insns/insn_lhu.py deleted file mode 100644 index 0f1c722..0000000 --- a/insns/insn_lhu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LHU instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(16) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b101) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lui.py b/insns/insn_lui.py deleted file mode 100644 index 73aa428..0000000 --- a/insns/insn_lui.py +++ /dev/null @@ -1,26 +0,0 @@ -from insn_U_type import * - -class rvfi_insn_lui(rvfi_insn_U_type): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN) - def ports(self): - return super(rvfi_insn_lui, self).ports() - def elaborate(self, platform): - m = super(rvfi_insn_lui, self).elaborate(platform) - - # LUI instruction - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111)) - m.d.comb += self.spec_rd_addr.eq(self.insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs1_addr.eq(0) - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~self.misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_lw.py b/insns/insn_lw.py deleted file mode 100644 index 4507283..0000000 --- a/insns/insn_lw.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_lw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # LW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - result = Signal(32) - m.d.comb += result.eq(self.rvfi_mem_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (insn_funct3 == 0b010) & (insn_opcode == 0b0000011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_rmask.eq((1 << 4) - 1) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mul.py b/insns/insn_mul.py deleted file mode 100644 index 2e45dfd..0000000 --- a/insns/insn_mul.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mul(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MUL instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x2cdf52a55876063e) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulh.py b/insns/insn_mulh.py deleted file mode 100644 index 05c93b6..0000000 --- a/insns/insn_mulh.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULH instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0x15d01651f6583fb7) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulhsu.py b/insns/insn_mulhsu.py deleted file mode 100644 index f8e957c..0000000 --- a/insns/insn_mulhsu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulhsu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULHSU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xea3969edecfbe137) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_mulhu.py b/insns/insn_mulhu.py deleted file mode 100644 index 685a6c3..0000000 --- a/insns/insn_mulhu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_mulhu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # MULHU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xd13db50d949ce5e8) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata + self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_or.py b/insns/insn_or.py deleted file mode 100644 index 85ca004..0000000 --- a/insns/insn_or.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_or(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # OR instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata | self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_ori.py b/insns/insn_ori.py deleted file mode 100644 index e4f8683..0000000 --- a/insns/insn_ori.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_ori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # ORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata | insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b110) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_rem.py b/insns/insn_rem.py deleted file mode 100644 index 3feba03..0000000 --- a/insns/insn_rem.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_rem(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # REM instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xf5b7d8538da68fa5) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b110) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_remu.py b/insns/insn_remu.py deleted file mode 100644 index 068ac62..0000000 --- a/insns/insn_remu.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_remu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # REMU instruction - altops_bitmask = Signal(64) - m.d.comb += altops_bitmask.eq(0xbc4402413138d0e1) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ altops_bitmask) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000001) & (insn_funct3 == 0b111) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sb.py b/insns/insn_sb.py deleted file mode 100644 index e7a25b6..0000000 --- a/insns/insn_sb.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sb(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SB instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b000) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 1) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_sh.py b/insns/insn_sh.py deleted file mode 100644 index f85446b..0000000 --- a/insns/insn_sh.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sh(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SH instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b001) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_sll.py b/insns/insn_sll.py deleted file mode 100644 index 08377af..0000000 --- a/insns/insn_sll.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_sll(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slli.py b/insns/insn_slli.py deleted file mode 100644 index 5c6cf43..0000000 --- a/insns/insn_slli.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_slli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata << insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b001) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slt.py b/insns/insn_slt.py deleted file mode 100644 index e3ec0e2..0000000 --- a/insns/insn_slt.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_slt(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLT instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b010) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_slti.py b/insns/insn_slti.py deleted file mode 100644 index 01e2863..0000000 --- a/insns/insn_slti.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_slti(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(insn_imm)) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sltiu.py b/insns/insn_sltiu.py deleted file mode 100644 index 2f1a005..0000000 --- a/insns/insn_sltiu.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sltiu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTIU instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata < insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b011) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sltu.py b/insns/insn_sltu.py deleted file mode 100644 index 810f4e7..0000000 --- a/insns/insn_sltu.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_sltu(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SLTU instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata < self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b011) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sra.py b/insns/insn_sra.py deleted file mode 100644 index a3c3d04..0000000 --- a/insns/insn_sra.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_sra(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRA instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srai.py b/insns/insn_srai.py deleted file mode 100644 index a9c4efb..0000000 --- a/insns/insn_srai.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_srai(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRAI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq((self.rvfi_rs1_rdata >> insn_shamt) | (-(self.rvfi_rs1_rdata < 0) << (self.RISCV_FORMAL_XLEN - insn_shamt))) # https://stackoverflow.com/a/25207042 - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b010000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srl.py b/insns/insn_srl.py deleted file mode 100644 index e72766a..0000000 --- a/insns/insn_srl.py +++ /dev/null @@ -1,88 +0,0 @@ -from nmigen import * - -class rvfi_insn_srl(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRL instruction - shamt = Signal(6) - m.d.comb += shamt.eq(Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_srli.py b/insns/insn_srli.py deleted file mode 100644 index d8fdc27..0000000 --- a/insns/insn_srli.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_srli(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format (shift variation) - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct6 = Signal(7) - m.d.comb += insn_funct6.eq(self.rvfi_insn[26:32]) - insn_shamt = Signal(6) - m.d.comb += insn_shamt.eq(self.rvfi_insn[20:26]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SRLI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata >> insn_shamt) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct6 == 0b000000) & (insn_funct3 == 0b101) & (insn_opcode == 0b0010011) & ((~insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64))) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sub.py b/insns/insn_sub.py deleted file mode 100644 index a1dc233..0000000 --- a/insns/insn_sub.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_sub(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SUB instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0100000) & (insn_funct3 == 0b000) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_sw.py b/insns/insn_sw.py deleted file mode 100644 index e96ec3f..0000000 --- a/insns/insn_sw.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_sw(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # S-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32]))) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # SW instruction - addr = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += addr.eq(self.rvfi_rs1_rdata + insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b010) & (insn_opcode == 0b0100011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_mem_addr.eq(addr) - m.d.comb += self.spec_mem_wmask.eq((1 << 4) - 1) - m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - m.d.comb += self.spec_trap.eq(~misa_ok) - - # default assignments - m.d.comb += self.spec_rd_addr.eq(0) - m.d.comb += self.spec_rd_wdata.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - - return m diff --git a/insns/insn_xor.py b/insns/insn_xor.py deleted file mode 100644 index a713d20..0000000 --- a/insns/insn_xor.py +++ /dev/null @@ -1,86 +0,0 @@ -from nmigen import * - -class rvfi_insn_xor(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # R-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_funct7 = Signal(7) - m.d.comb += insn_funct7.eq(self.rvfi_insn[25:32]) - insn_rs2 = Signal(5) - m.d.comb += insn_rs2.eq(self.rvfi_insn[20:25]) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # XOR instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct7 == 0b0000000) & (insn_funct3 == 0b100) & (insn_opcode == 0b0110011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rs2_addr.eq(insn_rs2) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m diff --git a/insns/insn_xori.py b/insns/insn_xori.py deleted file mode 100644 index 19c69e0..0000000 --- a/insns/insn_xori.py +++ /dev/null @@ -1,84 +0,0 @@ -from nmigen import * - -class rvfi_insn_xori(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - return input_ports + output_ports - def elaborate(self, platform): - m = Module() - - # I-type instruction format - insn_padding = Signal(self.RISCV_FORMAL_ILEN) - m.d.comb += insn_padding.eq(self.rvfi_insn >> 32) - insn_imm = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[20:32])) - insn_rs1 = Signal(5) - m.d.comb += insn_rs1.eq(self.rvfi_insn[15:20]) - insn_funct3 = Signal(3) - m.d.comb += insn_funct3.eq(self.rvfi_insn[12:15]) - insn_rd = Signal(5) - m.d.comb += insn_rd.eq(self.rvfi_insn[7:12]) - insn_opcode = Signal(7) - m.d.comb += insn_opcode.eq(self.rvfi_insn[:7]) - - misa_ok = Signal(1) - m.d.comb += misa_ok.eq(1) - - # XORI instruction - result = Signal(self.RISCV_FORMAL_XLEN) - m.d.comb += result.eq(self.rvfi_rs1_rdata ^ insn_imm) - m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_funct3 == 0b100) & (insn_opcode == 0b0010011)) - m.d.comb += self.spec_rs1_addr.eq(insn_rs1) - m.d.comb += self.spec_rd_addr.eq(insn_rd) - m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) - m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) - - # default assignments - m.d.comb += self.spec_rs2_addr.eq(0) - m.d.comb += self.spec_trap.eq(~misa_ok) - m.d.comb += self.spec_mem_addr.eq(0) - m.d.comb += self.spec_mem_rmask.eq(0) - m.d.comb += self.spec_mem_wmask.eq(0) - m.d.comb += self.spec_mem_wdata.eq(0) - - return m