From aa47b866a159a0532746c78bfecc97355eab364c Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:54:46 +0800 Subject: [PATCH] Add AND instruction --- insns/insn_and.py | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 insns/insn_and.py diff --git a/insns/insn_and.py b/insns/insn_and.py new file mode 100644 index 0000000..4cf5a52 --- /dev/null +++ b/insns/insn_and.py @@ -0,0 +1,21 @@ +from insn_R import * + +class rvfi_insn_and(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_and, self).__init__() + def ports(self): + return super(rvfi_insn_and, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_and, self).elaborate(platform) + + # AND instruction + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata & self.rvfi_rs2_rdata) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b111) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m