From a9cff77a82285958ca35eba1616381422e43bdef Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 3 Aug 2020 14:44:33 +0800 Subject: [PATCH] Add I-type (shift variation) instruction format --- insns/insn_I_shift.py | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 insns/insn_I_shift.py diff --git a/insns/insn_I_shift.py b/insns/insn_I_shift.py new file mode 100644 index 0000000..45f2819 --- /dev/null +++ b/insns/insn_I_shift.py @@ -0,0 +1,38 @@ +from insn import * + +class rvfi_insn_I_shift(rvfi_insn): + def __init__(self): + super(rvfi_insn_I_shift, self).__init__() + self.insn_padding = Signal(32) + self.insn_funct6 = Signal(7) + self.insn_shamt = Signal(6) + self.insn_rs1 = Signal(5) + self.insn_funct3 = Signal(3) + self.insn_rd = Signal(5) + self.insn_opcode = Signal(7) + self.misa_ok = Signal(1) + def ports(self): + return super(rvfi_insn_I_shift, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_I_shift, self).elaborate(platform) + + # I-type instruction format (shift variation) + m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32) + m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32]) + m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26]) + m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20]) + m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15]) + m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12]) + m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7]) + + m.d.comb += self.misa_ok.eq(1) + + # default assignments + m.d.comb += self.spec_rs2_addr.eq(0) + m.d.comb += self.spec_trap.eq(~self.misa_ok) + m.d.comb += self.spec_mem_addr.eq(0) + m.d.comb += self.spec_mem_rmask.eq(0) + m.d.comb += self.spec_mem_wmask.eq(0) + m.d.comb += self.spec_mem_wdata.eq(0) + + return m