diff --git a/insns/insn_UJ_type.py b/insns/insn_UJ_type.py
new file mode 100644
index 0000000..137d8be
--- /dev/null
+++ b/insns/insn_UJ_type.py
@@ -0,0 +1,34 @@
+from insn_general import *
+
+class rvfi_insn_UJ_type(rvfi_insn_general):
+    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
+        super(rvfi_insn_UJ_type, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
+        self.insn_padding = Signal(self.RISCV_FORMAL_ILEN)
+        self.insn_imm = Signal(self.RISCV_FORMAL_XLEN)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+        self.ialign16 = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_UJ_type, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_UJ_type, self).elaborate(platform)
+
+        # UJ-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[21:31], self.rvfi_insn[20], self.rvfi_insn[12:20], self.rvfi_insn[31]) << 1))
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+        m.d.comb += self.ialign16.eq(0)
+
+        # default assignments
+        m.d.comb += self.spec_rs1_addr.eq(0)
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m