From a78309d9970739e802c9ac24822694f576ab1ee9 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Tue, 11 Aug 2020 14:52:59 +0800
Subject: [PATCH] Add SW instruction

---
 insns/InsnSw.py | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 insns/InsnSw.py

diff --git a/insns/InsnSw.py b/insns/InsnSw.py
new file mode 100644
index 0000000..904a427
--- /dev/null
+++ b/insns/InsnSw.py
@@ -0,0 +1,9 @@
+from InsnRV32ISType import *
+
+"""
+SW instruction
+"""
+
+class InshSw(InsnRV32ISType):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, 0b010, 4)