From a6a09ac1209048d7b048574e34f8aca990a7f480 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Tue, 4 Aug 2020 12:31:36 +0800 Subject: [PATCH] Add SLL instruction --- insns/insn_sll.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 insns/insn_sll.py diff --git a/insns/insn_sll.py b/insns/insn_sll.py new file mode 100644 index 0000000..5158983 --- /dev/null +++ b/insns/insn_sll.py @@ -0,0 +1,23 @@ +from insn_R import * + +class rvfi_insn_sll(rvfi_insn_R): + def __init__(self): + super(rvfi_insn_sll, self).__init__() + def ports(self): + return super(rvfi_insn_sll, self).ports() + def elaborate(self, platform): + m = super(rvfi_insn_sll, self).elaborate(platform) + + # SLL instruction + shamt = Signal(6) + m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5]) + result = Signal(32) + m.d.comb += result.eq(self.rvfi_rs1_rdata << shamt) + m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0000000) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0110011)) + m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1) + m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2) + m.d.comb += self.spec_rd_addr.eq(self.insn_rd) + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0)) + m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) + + return m