From a58842ea9407125395b8c0e95a3dd7e8dae4b23e Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Wed, 26 Aug 2020 16:39:17 +0800 Subject: [PATCH] Add MULHSU instruction --- rvfi/insns/insn_mulh.py | 4 ++++ rvfi/insns/insn_mulhsu.py | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 rvfi/insns/insn_mulhsu.py diff --git a/rvfi/insns/insn_mulh.py b/rvfi/insns/insn_mulh.py index 0998752..8175f58 100644 --- a/rvfi/insns/insn_mulh.py +++ b/rvfi/insns/insn_mulh.py @@ -1,5 +1,9 @@ from .insn_rv32m_r_type import * +""" +MULH instruction +""" + class InsnMulh(InsnRV32MRType): def __init__(self, params): super().__init__(params, 0b001) diff --git a/rvfi/insns/insn_mulhsu.py b/rvfi/insns/insn_mulhsu.py new file mode 100644 index 0000000..a5ffca7 --- /dev/null +++ b/rvfi/insns/insn_mulhsu.py @@ -0,0 +1,18 @@ +from .insn_rv32m_r_type import * + +""" +MULHSU instruction +""" + +class InsnMulhsu(InsnRV32MRType): + def __init__(self, params): + super().__init__(params, 0b010) + def elaborate(self, platform): + m = super().elaborate(platform) + + if self.params.altops: + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0xea3969edecfbe137, 0)) + else: + m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (((Mux(self.rvfi_rs1_rdata[-1], 2 ** self.params.xlen - 1, 0) << self.params.xlen) | self.rvfi_rs1_rdata) * self.rvfi_rs2_rdata) >> self.params.xlen, 0)) + + return m