From a3a9592c194896b47e28203e10ee3568ffb49144 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Tue, 4 Aug 2020 12:47:35 +0800
Subject: [PATCH] Add SRA instruction
---
insns/insn_sra.py | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 insns/insn_sra.py
diff --git a/insns/insn_sra.py b/insns/insn_sra.py
new file mode 100644
index 0000000..c3075d9
--- /dev/null
+++ b/insns/insn_sra.py
@@ -0,0 +1,23 @@
+from insn_R import *
+
+class rvfi_insn_sra(rvfi_insn_R):
+ def __init__(self):
+ super(rvfi_insn_sra, self).__init__()
+ def ports(self):
+ return super(rvfi_insn_sra, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_sra, self).elaborate(platform)
+
+ # SRA instruction
+ shamt = Signal(6)
+ m.d.comb += shamt.eq(self.rvfi_rs2_rdata[:5])
+ result = Signal(32)
+ m.d.comb += result.eq((self.rvfi_rs1_rdata >> shamt) | (-(self.rvfi_rs1_rdata < 0) << (32 - shamt))) # https://stackoverflow.com/a/25207042
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct7 == 0b0100000) & (self.insn_funct3 == 0b101) & (self.insn_opcode == 0b0110011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
+ m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+
+ return m