From 9f6c634f4ac7a30fbf250910c9e4b0722f9d07cf Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Thu, 13 Aug 2020 12:19:40 +0800 Subject: [PATCH] Update README.md --- insns/IsaRV32I.py | 103 ---------------------------------------- insns/IsaRV32IGen.py | 110 ------------------------------------------- insns/README.md | 16 ++++++- 3 files changed, 15 insertions(+), 214 deletions(-) delete mode 100644 insns/IsaRV32I.py delete mode 100644 insns/IsaRV32IGen.py diff --git a/insns/IsaRV32I.py b/insns/IsaRV32I.py deleted file mode 100644 index c66a33d..0000000 --- a/insns/IsaRV32I.py +++ /dev/null @@ -1,103 +0,0 @@ -# Generated by IsaRV32IGen.py -from InsnLui import * -from InsnAuipc import * -from InsnJal import * -from InsnJalr import * -from InsnBeq import * -from InsnBne import * -from InsnBlt import * -from InsnBge import * -from InsnBltu import * -from InsnBgeu import * -from InsnLb import * -from InsnLh import * -from InsnLw import * -from InsnLbu import * -from InsnLhu import * -from InsnSb import * -from InsnSh import * -from InsnSw import * -from InsnAddi import * -from InsnSlti import * -from InsnSltiu import * -from InsnXori import * -from InsnOri import * -from InsnAndi import * -from InsnSlli import * -from InsnSrli import * -from InsnSrai import * -from InsnAdd import * -from InsnSub import * -from InsnSll import * -from InsnSlt import * -from InsnSltu import * -from InsnXor import * -from InsnSrl import * -from InsnSra import * -from InsnOr import * -from InsnAnd import * - -""" -RV32I Base ISA -""" - -class IsaRV32I(Elaboratable): - def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA): - # Core-specific constants - self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN - self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN - self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA - - # Input ports - self.rvfi_valid = Signal(1) - self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN) - self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN) - self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN) - if self.RISCV_FORMAL_CSR_MISA: - self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN) - - # Output ports - if self.RISCV_FORMAL_CSR_MISA: - self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN) - self.spec_valid = Signal(1) - self.spec_trap = Signal(1) - self.spec_rs1_addr = Signal(5) - self.spec_rs2_addr = Signal(5) - self.spec_rd_addr = Signal(5) - self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN) - self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8)) - self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN) - def ports(self): - input_ports = [ - self.rvfi_valid, - self.rvfi_insn, - self.rvfi_pc_rdata, - self.rvfi_rs1_rdata, - self.rvfi_rs2_rdata, - self.rvfi_mem_rdata - ] - if self.RISCV_FORMAL_CSR_MISA: - input_ports.append(self.rvfi_csr_misa_rdata) - output_ports = [ - self.spec_valid, - self.spec_trap, - self.spec_rs1_addr, - self.spec_rs2_addr, - self.spec_rd_addr, - self.spec_rd_wdata, - self.spec_pc_wdata, - self.spec_mem_addr, - self.spec_mem_rmask, - self.spec_mem_wmask, - self.spec_mem_wdata - ] - if self.RISCV_FORMAL_CSR_MISA: - output_ports.append(self.spec_csr_misa_rmask) - return input_ports + output_ports - def elaborate(self, platform): - pass diff --git a/insns/IsaRV32IGen.py b/insns/IsaRV32IGen.py deleted file mode 100644 index 4383bae..0000000 --- a/insns/IsaRV32IGen.py +++ /dev/null @@ -1,110 +0,0 @@ -RV32I_INSNS = [ - 'lui', - 'auipc', - 'jal', - 'jalr', - 'beq', - 'bne', - 'blt', - 'bge', - 'bltu', - 'bgeu', - 'lb', - 'lh', - 'lw', - 'lbu', - 'lhu', - 'sb', - 'sh', - 'sw', - 'addi', - 'slti', - 'sltiu', - 'xori', - 'ori', - 'andi', - 'slli', - 'srli', - 'srai', - 'add', - 'sub', - 'sll', - 'slt', - 'sltu', - 'xor', - 'srl', - 'sra', - 'or', - 'and' -] - -if __name__ == '__main__': - print('# Generated by IsaRV32IGen.py') - for insn in RV32I_INSNS: - print('from Insn%s import *' % insn.capitalize()) - print() - print('"""') - print('RV32I Base ISA') - print('"""') - print() - print('class IsaRV32I(Elaboratable):') - print(' def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA):') - print(' # Core-specific constants') - print(' self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN') - print(' self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN') - print(' self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA') - print() - print(' # Input ports') - print(' self.rvfi_valid = Signal(1)') - print(' self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)') - print(' self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)') - print() - print(' # Output ports') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' self.spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_valid = Signal(1)') - print(' self.spec_trap = Signal(1)') - print(' self.spec_rs1_addr = Signal(5)') - print(' self.spec_rs2_addr = Signal(5)') - print(' self.spec_rd_addr = Signal(5)') - print(' self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)') - print(' self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') - print(' self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))') - print(' self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)') - print(' def ports(self):') - print(' input_ports = [') - print(' self.rvfi_valid,') - print(' self.rvfi_insn,') - print(' self.rvfi_pc_rdata,') - print(' self.rvfi_rs1_rdata,') - print(' self.rvfi_rs2_rdata,') - print(' self.rvfi_mem_rdata') - print(' ]') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' input_ports.append(self.rvfi_csr_misa_rdata)') - print(' output_ports = [') - print(' self.spec_valid,') - print(' self.spec_trap,') - print(' self.spec_rs1_addr,') - print(' self.spec_rs2_addr,') - print(' self.spec_rd_addr,') - print(' self.spec_rd_wdata,') - print(' self.spec_pc_wdata,') - print(' self.spec_mem_addr,') - print(' self.spec_mem_rmask,') - print(' self.spec_mem_wmask,') - print(' self.spec_mem_wdata') - print(' ]') - print(' if self.RISCV_FORMAL_CSR_MISA:') - print(' output_ports.append(self.spec_csr_misa_rmask)') - print(' return input_ports + output_ports') - print(' def elaborate(self, platform):') - print(' pass') - # TODO diff --git a/insns/README.md b/insns/README.md index 7f2d35f..ca395c1 100644 --- a/insns/README.md +++ b/insns/README.md @@ -34,6 +34,8 @@ Below is a table of RISC-V instructions supported by the original riscv-formal f ## Class Synopsis +### Instructions + Below is a list of instructions currently supported by this port of the riscv-formal framework and is expected to grow over time. The instructions are roughly grouped by instruction type but sometimes with further specializations - the hierarchy of the lists reflects the hierarchy of inheritance in the classes used to represent various instructions. - `Insn`: General RISC-V instruction @@ -83,6 +85,18 @@ Below is a list of instructions currently supported by this port of the riscv-fo - `InsnLui`: LUI instruction - `InsnAuipc`: AUIPC instruction -## Parameters +### ISAs TODO + +## Core-specific constants + +The following core-specific constants are currently supported: + +| Constant | Description | Valid value(s) | Supported by instruction(s) | +| --- | --- | --- | --- | +| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` | LUI, AUIPC, JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND | +| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` | JAL, JALR, BEQ, BNE, BLT, BGE, BLTU, BGEU | +| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` | LB, LH, LW, LBU, LHU, SB, SH, SW |