From 9cbed8f1473f576c78ec95cdbc04e29d7e6d05d2 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Fri, 31 Jul 2020 13:29:48 +0800
Subject: [PATCH] Add U-type instruction class

---
 insns/insn_U.py | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 insns/insn_U.py

diff --git a/insns/insn_U.py b/insns/insn_U.py
new file mode 100644
index 0000000..aec6828
--- /dev/null
+++ b/insns/insn_U.py
@@ -0,0 +1,33 @@
+from insn import *
+
+class rvfi_insn_U(rvfi_insn):
+    def __init__(self):
+        super(rvfi_insn_U, self).__init__()
+        self.insn_padding = Signal(32)
+        self.insn_imm = Signal(32)
+        self.insn_rd = Signal(5)
+        self.insn_opcode = Signal(7)
+        self.misa_ok = Signal(1)
+    def ports(self):
+        return super(rvfi_insn_U, self).ports()
+    def elaborate(self, platform):
+        m = super(rvfi_insn_U, self).elaborate(platform)
+
+        # U-type instruction format
+        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
+        m.d.comb += self.insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
+        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
+        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
+
+        m.d.comb += self.misa_ok.eq(1)
+
+        # Default assignments
+        m.d.comb += self.spec_rs1_addr.eq(0)
+        m.d.comb += self.spec_rs2_addr.eq(0)
+        m.d.comb += self.spec_trap.eq(~self.misa_ok)
+        m.d.comb += self.spec_mem_addr.eq(0)
+        m.d.comb += self.spec_mem_rmask.eq(0)
+        m.d.comb += self.spec_mem_wmask.eq(0)
+        m.d.comb += self.spec_mem_wdata.eq(0)
+
+        return m