From 9740470c47d05f786d230f91da8a9744e645df2e Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Mon, 10 Aug 2020 12:35:49 +0800
Subject: [PATCH] Add SRLI instruction

---
 insns/InsnSrli.py | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 insns/InsnSrli.py

diff --git a/insns/InsnSrli.py b/insns/InsnSrli.py
new file mode 100644
index 0000000..cb678ba
--- /dev/null
+++ b/insns/InsnSrli.py
@@ -0,0 +1,15 @@
+from InsnRV32IITypeShift import *
+
+"""
+SRLI instruction
+"""
+
+class InsnSrli(InsnRV32IITypeShift):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000000, 0b101)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> self.insn_shamt, 0))
+
+        return m