From 94faa3ba680804d26dd75bba9aa51d630650b568 Mon Sep 17 00:00:00 2001 From: Donald Sebastian Leung Date: Mon, 10 Aug 2020 11:15:05 +0800 Subject: [PATCH] Remove redundancy in super() calls --- insns/InsnAdd.py | 4 ++-- insns/InsnAnd.py | 4 ++-- insns/InsnOr.py | 4 ++-- insns/InsnRV32IITypeShift.py | 4 ++-- insns/InsnRV32IRType.py | 4 ++-- insns/InsnSll.py | 4 ++-- insns/InsnSlt.py | 4 ++-- insns/InsnSltu.py | 4 ++-- insns/InsnSra.py | 4 ++-- insns/InsnSrl.py | 4 ++-- insns/InsnSub.py | 4 ++-- insns/InsnXor.py | 4 ++-- 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/insns/InsnAdd.py b/insns/InsnAdd.py index 018afbc..d495fe0 100644 --- a/insns/InsnAdd.py +++ b/insns/InsnAdd.py @@ -6,9 +6,9 @@ ADD instruction class InsnAdd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnAdd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b000, 0b0110011) def elaborate(self, platform): - m = super(InsnAdd, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnAnd.py b/insns/InsnAnd.py index e0f4adb..b874914 100644 --- a/insns/InsnAnd.py +++ b/insns/InsnAnd.py @@ -6,9 +6,9 @@ AND instruction class InsnAnd(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnAnd, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b111, 0b0110011) def elaborate(self, platform): - m = super(InsnAnd, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata & self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnOr.py b/insns/InsnOr.py index 1470644..ed832a0 100644 --- a/insns/InsnOr.py +++ b/insns/InsnOr.py @@ -6,9 +6,9 @@ OR instruction class InsnOr(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnOr, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b110, 0b0110011) def elaborate(self, platform): - m = super(InsnOr, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata | self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnRV32IITypeShift.py b/insns/InsnRV32IITypeShift.py index ab28f2c..62f6403 100644 --- a/insns/InsnRV32IITypeShift.py +++ b/insns/InsnRV32IITypeShift.py @@ -6,11 +6,11 @@ RV32I I-Type Instruction (Shift Variation) class InsnRV32IITypeShift(Insn): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct6, funct3): - super(InsnRV32IITypeShift, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) self.funct6 = funct6 self.funct3 = funct3 def elaborate(self, platform): - m = super(InsnRV32IITypeShift, self).elaborate(platform) + m = super().elaborate(platform) if self.RISCV_FORMAL_CSR_MISA: m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) diff --git a/insns/InsnRV32IRType.py b/insns/InsnRV32IRType.py index f990e53..c14dabd 100644 --- a/insns/InsnRV32IRType.py +++ b/insns/InsnRV32IRType.py @@ -6,12 +6,12 @@ RV32I R-Type Instruction class InsnRV32IRType(Insn): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, funct7, funct3, opcode): - super(InsnRV32IRType, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED) self.funct7 = funct7 self.funct3 = funct3 self.opcode = opcode def elaborate(self, platform): - m = super(InsnRV32IRType, self).elaborate(platform) + m = super().elaborate(platform) if self.RISCV_FORMAL_CSR_MISA: m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0) diff --git a/insns/InsnSll.py b/insns/InsnSll.py index bb99acb..5b55dbf 100644 --- a/insns/InsnSll.py +++ b/insns/InsnSll.py @@ -6,9 +6,9 @@ SLL instruction class InsnSll(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSll, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b001, 0b0110011) def elaborate(self, platform): - m = super(InsnSll, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) diff --git a/insns/InsnSlt.py b/insns/InsnSlt.py index 4f2be0f..89807ea 100644 --- a/insns/InsnSlt.py +++ b/insns/InsnSlt.py @@ -6,9 +6,9 @@ SLT instruction class InsnSlt(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSlt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b010, 0b0110011) def elaborate(self, platform): - m = super(InsnSlt, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata), 0)) diff --git a/insns/InsnSltu.py b/insns/InsnSltu.py index 318f717..ff9f3ec 100644 --- a/insns/InsnSltu.py +++ b/insns/InsnSltu.py @@ -6,9 +6,9 @@ SLTU instruction class InsnSltu(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSltu, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b011, 0b0110011) def elaborate(self, platform): - m = super(InsnSltu, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata < self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnSra.py b/insns/InsnSra.py index bbdc626..0b1f133 100644 --- a/insns/InsnSra.py +++ b/insns/InsnSra.py @@ -6,9 +6,9 @@ SRA instruction class InsnSra(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSra, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b101, 0b0110011) def elaborate(self, platform): - m = super(InsnSra, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) diff --git a/insns/InsnSrl.py b/insns/InsnSrl.py index ad93d47..f68164c 100644 --- a/insns/InsnSrl.py +++ b/insns/InsnSrl.py @@ -6,9 +6,9 @@ SRL instruction class InsnSrl(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSrl, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): - m = super(InsnSrl, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0)) diff --git a/insns/InsnSub.py b/insns/InsnSub.py index d8bf5fd..b5435d8 100644 --- a/insns/InsnSub.py +++ b/insns/InsnSub.py @@ -6,9 +6,9 @@ SUB instruction class InsnSub(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnSub, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0100000, 0b000, 0b0110011) def elaborate(self, platform): - m = super(InsnSub, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata - self.rvfi_rs2_rdata, 0)) diff --git a/insns/InsnXor.py b/insns/InsnXor.py index 58c4978..0569fa7 100644 --- a/insns/InsnXor.py +++ b/insns/InsnXor.py @@ -6,9 +6,9 @@ XOR instruction class InsnXor(InsnRV32IRType): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): - super(InsnXor, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) + super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b0000000, 0b100, 0b0110011) def elaborate(self, platform): - m = super(InsnXor, self).elaborate(platform) + m = super().elaborate(platform) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata ^ self.rvfi_rs2_rdata, 0))