From 948a3db1c1bfbb7fe62a77ad6937b99a3bb7bcc5 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Mon, 3 Aug 2020 14:27:08 +0800
Subject: [PATCH] Add SH instruction
---
insns/insn_sh.py | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 insns/insn_sh.py
diff --git a/insns/insn_sh.py b/insns/insn_sh.py
new file mode 100644
index 0000000..1a246c5
--- /dev/null
+++ b/insns/insn_sh.py
@@ -0,0 +1,23 @@
+from insn_S import *
+
+class rvfi_insn_sh(rvfi_insn_S):
+ def __init__(self):
+ super(rvfi_insn_sh, self).__init__()
+ def ports(self):
+ return super(rvfi_insn_sh, self).ports()
+ def elaborate(self, platform):
+ m = super(rvfi_insn_sh, self).elaborate(platform)
+
+ # SH instruction
+ addr = Signal(32)
+ m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0100011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_mem_addr.eq(addr)
+ m.d.comb += self.spec_mem_wmask.eq((1 << 2) - 1)
+ m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+ return m