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riscv-formal-nmigen
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Refactor LUI instruction

This commit is contained in:
Donald Sebastian Leung 2020-07-30 12:55:57 +08:00
parent 34c8b6cf3d
commit 927c12e97c
1 changed files with 8 additions and 69 deletions
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77
insns/insn_lui.py
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@ -1,78 +1,17 @@
from nmigen import * from insn_U_type import *
class rvfi_insn_lui(Elaboratable): class rvfi_insn_lui(rvfi_insn_U_type):
def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32): def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN super(rvfi_insn_lui, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
self.rvfi_valid = Signal(1)
self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_valid = Signal(1)
self.spec_trap = Signal(1)
self.spec_rs1_addr = Signal(5)
self.spec_rs2_addr = Signal(5)
self.spec_rd_addr = Signal(5)
self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
def ports(self): def ports(self):
input_ports = [ return super(rvfi_insn_lui, self).ports()
self.rvfi_valid,
self.rvfi_insn,
self.rvfi_pc_rdata,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_mem_rdata
]
output_ports = [
self.spec_valid,
self.spec_trap,
self.spec_rs1_addr,
self.spec_rs2_addr,
self.spec_rd_addr,
self.spec_rd_wdata,
self.spec_pc_wdata,
self.spec_mem_addr,
self.spec_mem_rmask,
self.spec_mem_wmask,
self.spec_mem_wdata
]
return input_ports + output_ports
def elaborate(self, platform): def elaborate(self, platform):
m = Module() m = super(rvfi_insn_lui, self).elaborate(platform)
# U-type instruction format
insn_padding = Signal(self.RISCV_FORMAL_ILEN)
m.d.comb += insn_padding.eq(self.rvfi_insn >> 32)
insn_imm = Signal(self.RISCV_FORMAL_XLEN)
m.d.comb += insn_imm.eq(Value.as_signed(self.rvfi_insn[12:32] << 12))
insn_rd = Signal(5)
m.d.comb += insn_rd.eq(self.rvfi_insn[7:12])
insn_opcode = Signal(7)
m.d.comb += insn_opcode.eq(self.rvfi_insn[:7])
misa_ok = Signal(1)
m.d.comb += misa_ok.eq(1)
# LUI instruction # LUI instruction
m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~insn_padding) & (insn_opcode == 0b0110111)) m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_opcode == 0b0110111))
m.d.comb += self.spec_rd_addr.eq(insn_rd) m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, insn_imm, 0)) m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.insn_imm, 0))
m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4) m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
# default assignments
m.d.comb += self.spec_rs1_addr.eq(0)
m.d.comb += self.spec_rs2_addr.eq(0)
m.d.comb += self.spec_trap.eq(~misa_ok)
m.d.comb += self.spec_mem_addr.eq(0)
m.d.comb += self.spec_mem_rmask.eq(0)
m.d.comb += self.spec_mem_wmask.eq(0)
m.d.comb += self.spec_mem_wdata.eq(0)
return m return m