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riscv-formal-nmigen
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Add SLTI instruction

This commit is contained in:
Donald Sebastian Leung 2020-08-10 17:24:50 +08:00
parent 0ae11e12b5
commit 84f4b75267
2 changed files with 19 additions and 0 deletions
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4
insns/InsnAddi.py
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@ -1,5 +1,9 @@
from InsnRV32IITypeArith import * from InsnRV32IITypeArith import *
"""
ADDI instruction
"""
class InsnAddi(InsnRV32IITypeArith): class InsnAddi(InsnRV32IITypeArith):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED): def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000) super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)

15
insns/InsnSlti.py Normal file
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@ -0,0 +1,15 @@
from InsnRV32IITypeArith import *
"""
SLTI instruction
"""
class InsnSlti(InsnRV32IITypeArith):
def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010)
def elaborate(self, platform):
m = super().elaborate(platform)
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm), 0))
return m