diff --git a/insns/InsnAddi.py b/insns/InsnAddi.py
index 8c4aa99..85abc02 100644
--- a/insns/InsnAddi.py
+++ b/insns/InsnAddi.py
@@ -1,5 +1,9 @@
 from InsnRV32IITypeArith import *
 
+"""
+ADDI instruction
+"""
+
 class InsnAddi(InsnRV32IITypeArith):
     def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
         super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b000)
diff --git a/insns/InsnSlti.py b/insns/InsnSlti.py
new file mode 100644
index 0000000..07b4b52
--- /dev/null
+++ b/insns/InsnSlti.py
@@ -0,0 +1,15 @@
+from InsnRV32IITypeArith import *
+
+"""
+SLTI instruction
+"""
+
+class InsnSlti(InsnRV32IITypeArith):
+    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED):
+        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, 0b010)
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.insn_imm), 0))
+
+        return m