diff --git a/README.md b/README.md
index 271ce33..e08822d 100644
--- a/README.md
+++ b/README.md
@@ -10,7 +10,7 @@ A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
 
 TODO
 
-## Support
+## Scope
 
 The full [RISC-V specification](https://riscv.org/specifications/) is hundreds of pages long including numerous possible extensions, some of which are still under active development at the time of writing. Therefore, this project does not aim to formalize the entire specification, but only the core parts of the specification, namely RV32I (except FENCE, ECALL and EBREAK) and perhaps RV32IM. Support for other extensions of the RISC-V specification may be added in the future.
 
diff --git a/insns/README.md b/insns/README.md
new file mode 100644
index 0000000..034ebc4
--- /dev/null
+++ b/insns/README.md
@@ -0,0 +1,28 @@
+# RISC-V Instructions
+
+Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*.
+
+| Instruction type | Instructions |
+| --- | --- |
+| U-type | lui, auipc |
+| UJ-type | jal |
+| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi |
+| SB-type | beq, bne, blt, bge, bltu, bgeu |
+| S-type | sb, sh, sw |
+| I-type (shift variation) | slli, srli, srai |
+| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu |
+
+\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks.
+
+## Caveats
+
+At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation:
+
+| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen |
+| --- | --- |
+| `RISCV_FORMAL_ILEN` | 32 |
+| `RISCV_FORMAL_XLEN` | 32 |
+| `RISCV_FORMAL_CSR_MISA` | undefined |
+| `RISCV_FORMAL_COMPRESSED` | undefined |
+| `RISCV_FORMAL_ALIGNED_MEM` | undefined |
+| `RISCV_FORMAL_ALTOPS` | defined |